130 lines
4.0 KiB
Python
130 lines
4.0 KiB
Python
from migen.fhdl.decorators import ModuleTransformer
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from misoclib.com.liteeth.common import *
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# Generic classes
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class Port:
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def connect(self, port):
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r = [
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Record.connect(self.source, port.sink),
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Record.connect(port.source, self.sink)
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]
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return r
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# Generic modules
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class BufferizeEndpoints(ModuleTransformer):
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def __init__(self, *names):
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self.names = names
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def transform_instance(self, submodule):
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endpoints = get_endpoints(submodule)
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sinks = {}
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sources = {}
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for name, endpoint in endpoints.items():
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if not self.names or name in self.names:
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if isinstance(endpoint, Sink):
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sinks.update({name: endpoint})
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elif isinstance(endpoint, Source):
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sources.update({name: endpoint})
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# add buffer on sinks
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for name, sink in sinks.items():
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buf = Buffer(sink.description)
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submodule.submodules += buf
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setattr(self, name, buf.d)
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submodule.comb += Record.connect(buf.q, sink)
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# add buffer on sources
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for name, source in sources.items():
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buf = Buffer(source.description)
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submodule.submodules += buf
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submodule.comb += Record.connect(source, buf.d)
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setattr(self, name, buf.q)
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class EndpointPacketStatus(Module):
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def __init__(self, endpoint):
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self.start = Signal()
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self.done = Signal()
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self.ongoing = Signal()
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ongoing = Signal()
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self.comb += [
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self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
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self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
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]
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self.sync += \
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If(self.start,
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ongoing.eq(1)
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).Elif(self.done,
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ongoing.eq(0)
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)
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self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
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class PacketBuffer(Module):
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def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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# # #
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sink_status = EndpointPacketStatus(self.sink)
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source_status = EndpointPacketStatus(self.source)
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self.submodules += sink_status, source_status
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# store incoming packets
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# cmds
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def cmd_description():
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layout = [("error", 1)]
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return EndpointDescription(layout)
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cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.submodules += cmd_fifo
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self.comb += cmd_fifo.sink.stb.eq(sink_status.done)
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if hasattr(sink, "error"):
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self.comb += cmd_fifo.sink.error.eq(sink.error)
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# data
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data_fifo = SyncFIFO(description, data_depth, buffered=True)
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self.submodules += data_fifo
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self.comb += [
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Record.connect(self.sink, data_fifo.sink),
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data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
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self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
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]
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# output packets
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("SEEK_SOP")
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)
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)
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fsm.act("SEEK_SOP",
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If(~data_fifo.source.sop,
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data_fifo.source.ack.eq(1)
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).Else(
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NextState("OUTPUT")
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)
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)
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if hasattr(source, "error"):
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source_error = self.source.error
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else:
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source_error = Signal()
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fsm.act("OUTPUT",
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Record.connect(data_fifo.source, self.source),
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source_error.eq(cmd_fifo.source.error),
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If(source_status.done,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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# compute almost full
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if almost_full is not None:
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self.almost_full = Signal()
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self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
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