20 lines
639 B
Python
20 lines
639 B
Python
from migen.fhdl import verilog
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from migen.bus import wishbone
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m1 = wishbone.Interface()
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m2 = wishbone.Interface()
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s1 = wishbone.Interface()
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s2 = wishbone.Interface()
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wishbonecon0 = wishbone.InterconnectShared(
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[m1, m2],
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[(0, s1), (1, s2)],
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register=True,
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offset=1)
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frag = wishbonecon0.get_fragment()
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v = verilog.convert(frag, name="intercon", ios={m1.cyc, m1.stb, m1.we, m1.adr, m1.sel, m1.dat_w, m1.dat_r, m1.ack,
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m2.cyc, m2.stb, m2.we, m2.adr, m2.sel, m2.dat_r, m2.dat_w, m2.ack,
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s1.cyc, s1.stb, s1.we, s1.adr, s1.sel, s1.dat_r, s1.dat_w, s1.ack,
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s2.cyc, s2.stb, s2.we, s2.adr, s2.sel, s2.dat_r, s2.dat_w, s2.ack})
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print(v)
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