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litex/migen/fhdl
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Guy Hutchison 28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
..
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
bitcontainer.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00
conv_output.py introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
decorators.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00
edif.py global: pep8 (E231) 2015-04-13 20:50:03 +02:00
module.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00
namer.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00
simplify.py global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
specials.py global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
std.py global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
structure.py global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
tools.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00
tracer.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00
verilog.py fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
visit.py global: pep8 (E302) 2015-04-13 20:45:35 +02:00