litex/migen/bus
Sebastien Bourdeauducq 2b8dc52c13 Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
asmibus.py Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
csr.py csr/SRAM: support for writes with memory widths larger than bus words 2013-03-09 00:50:57 +01:00
dfi.py Remove Constant 2012-11-28 23:18:43 +01:00
memory.py bus: memory initiator 2012-11-23 16:22:50 +01:00
simple.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
transactions.py bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
wishbone.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
wishbone2asmi.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
wishbone2csr.py corelogic -> genlib 2013-02-22 23:19:37 +01:00