188 lines
7.9 KiB
Python
188 lines
7.9 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.bank.description import *
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class DataCapture(Module, AutoCSR):
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def __init__(self, pad_p, pad_n, ntbits):
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self.serdesstrobe = Signal()
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self.d = Signal(10)
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self._dly_ctl = CSR(6)
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self._dly_busy = CSRStatus(2)
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self._phase = CSRStatus(2)
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self._phase_reset = CSR()
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###
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# IO
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pad_se = Signal()
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self.specials += Instance("IBUFDS", i_I=pad_p, i_IB=pad_n, o_O=pad_se)
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pad_delayed_master = Signal()
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pad_delayed_slave = Signal()
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delay_inc = Signal()
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delay_ce = Signal()
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delay_master_cal = Signal()
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delay_master_rst = Signal()
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delay_master_busy = Signal()
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delay_slave_cal = Signal()
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delay_slave_rst = Signal()
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delay_slave_busy = Signal()
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self.specials += Instance("IODELAY2",
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p_SERDES_MODE="MASTER",
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p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR",
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p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
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i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_master,
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i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"),
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i_INC=delay_inc, i_CE=delay_ce,
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i_CAL=delay_master_cal, i_RST=delay_master_rst, o_BUSY=delay_master_busy,
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i_T=1)
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self.specials += Instance("IODELAY2",
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p_SERDES_MODE="SLAVE",
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p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR",
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p_COUNTER_WRAPAROUND="WRAPAROUND", p_DATA_RATE="SDR",
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i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_slave,
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i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"),
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i_INC=delay_inc, i_CE=delay_ce,
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i_CAL=delay_slave_cal, i_RST=delay_slave_rst, o_BUSY=delay_slave_busy,
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i_T=1)
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dsr2 = Signal(5)
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pd_valid = Signal()
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pd_incdec = Signal()
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pd_edge = Signal()
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pd_cascade = Signal()
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self.specials += Instance("ISERDES2",
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p_SERDES_MODE="MASTER",
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5,
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p_INTERFACE_TYPE="RETIMED",
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i_D=pad_delayed_master,
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o_Q4=dsr2[4], o_Q3=dsr2[3], o_Q2=dsr2[2], o_Q1=dsr2[1],
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i_BITSLIP=0, i_CE0=1, i_RST=0,
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i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"),
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i_IOCE=self.serdesstrobe,
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o_VALID=pd_valid, o_INCDEC=pd_incdec,
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i_SHIFTIN=pd_edge, o_SHIFTOUT=pd_cascade)
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self.specials += Instance("ISERDES2",
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p_SERDES_MODE="SLAVE",
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5,
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p_INTERFACE_TYPE="RETIMED",
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i_D=pad_delayed_slave,
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o_Q4=dsr2[0],
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i_BITSLIP=0, i_CE0=1, i_RST=0,
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i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"),
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i_IOCE=self.serdesstrobe,
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i_SHIFTIN=pd_cascade, o_SHIFTOUT=pd_edge)
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# Phase error accumulator
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lateness = Signal(ntbits, reset=2**(ntbits - 1))
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too_late = Signal()
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too_early = Signal()
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reset_lateness = Signal()
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self.comb += [
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too_late.eq(lateness == (2**ntbits - 1)),
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too_early.eq(lateness == 0)
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]
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self.sync.pix2x += [
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If(reset_lateness,
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lateness.eq(2**(ntbits - 1))
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).Elif(~delay_master_busy & ~delay_slave_busy & ~too_late & ~too_early,
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If(pd_valid & pd_incdec, lateness.eq(lateness - 1)),
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If(pd_valid & ~pd_incdec, lateness.eq(lateness + 1))
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)
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]
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# Delay control
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self.submodules.delay_master_done = PulseSynchronizer("pix2x", "sys")
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delay_master_pending = Signal()
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self.sync.pix2x += [
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self.delay_master_done.i.eq(0),
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If(~delay_master_pending,
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If(delay_master_cal | delay_ce, delay_master_pending.eq(1))
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).Else(
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If(~delay_master_busy,
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self.delay_master_done.i.eq(1),
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delay_master_pending.eq(0)
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)
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)
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]
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self.submodules.delay_slave_done = PulseSynchronizer("pix2x", "sys")
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delay_slave_pending = Signal()
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self.sync.pix2x += [
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self.delay_slave_done.i.eq(0),
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If(~delay_slave_pending,
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If(delay_slave_cal | delay_ce, delay_slave_pending.eq(1))
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).Else(
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If(~delay_slave_busy,
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self.delay_slave_done.i.eq(1),
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delay_slave_pending.eq(0)
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)
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)
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]
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self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix2x")
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self.comb += [
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delay_master_cal.eq(self.do_delay_master_cal.o),
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delay_master_rst.eq(self.do_delay_master_rst.o),
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delay_slave_cal.eq(self.do_delay_slave_cal.o),
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delay_slave_rst.eq(self.do_delay_slave_rst.o),
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delay_inc.eq(self.do_delay_inc.o),
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delay_ce.eq(self.do_delay_inc.o | self.do_delay_dec.o),
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]
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sys_delay_master_pending = Signal()
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self.sync += [
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If(self.do_delay_master_cal.i | self.do_delay_inc.i | self.do_delay_dec.i,
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sys_delay_master_pending.eq(1)
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).Elif(self.delay_master_done.o,
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sys_delay_master_pending.eq(0)
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)
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]
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sys_delay_slave_pending = Signal()
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self.sync += [
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If(self.do_delay_slave_cal.i | self.do_delay_inc.i | self.do_delay_dec.i,
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sys_delay_slave_pending.eq(1)
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).Elif(self.delay_slave_done.o,
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sys_delay_slave_pending.eq(0)
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)
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]
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self.comb += [
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self.do_delay_master_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[0]),
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self.do_delay_master_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[1]),
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self.do_delay_slave_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[2]),
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self.do_delay_slave_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[3]),
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self.do_delay_inc.i.eq(self._dly_ctl.re & self._dly_ctl.r[4]),
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self.do_delay_dec.i.eq(self._dly_ctl.re & self._dly_ctl.r[5]),
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self._dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
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]
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# Phase detector control
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self.specials += MultiReg(Cat(too_late, too_early), self._phase.status)
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self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x")
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self.comb += [
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reset_lateness.eq(self.do_reset_lateness.o),
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self.do_reset_lateness.i.eq(self._phase_reset.re)
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]
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# 5:10 deserialization
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dsr = Signal(10)
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self.sync.pix2x += dsr.eq(Cat(dsr[5:], dsr2))
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self.sync.pix += self.d.eq(dsr)
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