166 lines
3.9 KiB
Python
166 lines
3.9 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.record import Record
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from migen.genlib.fifo import AsyncFIFO
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.bank.description import CSRStorage
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from migen.actorlib import spi
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_hbits = 11
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_vbits = 12
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bpp = 32
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bpc = 10
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pixel_layout_s = [
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("pad", bpp-3*bpc),
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("r", bpc),
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("g", bpc),
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("b", bpc)
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]
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pixel_layout = [
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("p0", pixel_layout_s),
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("p1", pixel_layout_s)
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]
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bpc_dac = 8
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dac_layout_s = [
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("r", bpc_dac),
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("g", bpc_dac),
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("b", bpc_dac)
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]
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dac_layout = [
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("hsync", 1),
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("vsync", 1),
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("p0", dac_layout_s),
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("p1", dac_layout_s)
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]
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class FrameInitiator(spi.SingleGenerator):
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def __init__(self):
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layout = [
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("hres", _hbits, 640, 1),
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("hsync_start", _hbits, 656, 1),
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("hsync_end", _hbits, 752, 1),
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("hscan", _hbits, 800, 1),
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("vres", _vbits, 480),
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("vsync_start", _vbits, 492),
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("vsync_end", _vbits, 494),
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("vscan", _vbits, 525)
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]
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spi.SingleGenerator.__init__(self, layout, spi.MODE_EXTERNAL)
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class VTG(Module):
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def __init__(self):
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self.timing = Sink([
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("hres", _hbits),
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("hsync_start", _hbits),
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("hsync_end", _hbits),
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("hscan", _hbits),
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("vres", _vbits),
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("vsync_start", _vbits),
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("vsync_end", _vbits),
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("vscan", _vbits)])
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self.pixels = Sink(pixel_layout)
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self.dac = Source(dac_layout)
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self.busy = Signal()
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hactive = Signal()
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vactive = Signal()
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active = Signal()
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generate_en = Signal()
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hcounter = Signal(_hbits)
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vcounter = Signal(_vbits)
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skip = bpc - bpc_dac
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self.comb += [
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active.eq(hactive & vactive),
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If(active,
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[getattr(getattr(self.dac.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
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for p in ["p0", "p1"] for c in ["r", "g", "b"]]
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),
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generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
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self.pixels.ack.eq(self.dac.ack & active),
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self.dac.stb.eq(generate_en),
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self.busy.eq(generate_en)
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]
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tp = self.timing.payload
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self.sync += [
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self.timing.ack.eq(0),
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If(generate_en & self.dac.ack,
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hcounter.eq(hcounter + 1),
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If(hcounter == 0, hactive.eq(1)),
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If(hcounter == tp.hres, hactive.eq(0)),
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If(hcounter == tp.hsync_start, self.dac.payload.hsync.eq(1)),
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If(hcounter == tp.hsync_end, self.dac.payload.hsync.eq(0)),
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If(hcounter == tp.hscan,
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hcounter.eq(0),
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If(vcounter == tp.vscan,
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vcounter.eq(0),
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self.timing.ack.eq(1)
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).Else(
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vcounter.eq(vcounter + 1)
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)
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),
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If(vcounter == 0, vactive.eq(1)),
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If(vcounter == tp.vres, vactive.eq(0)),
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If(vcounter == tp.vsync_start, self.dac.payload.vsync.eq(1)),
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If(vcounter == tp.vsync_end, self.dac.payload.vsync.eq(0))
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)
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]
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class FIFO(Module):
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def __init__(self):
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self.dac = Sink(dac_layout)
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self.busy = Signal()
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self.vga_hsync_n = Signal()
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self.vga_vsync_n = Signal()
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self.vga_r = Signal(bpc_dac)
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self.vga_g = Signal(bpc_dac)
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self.vga_b = Signal(bpc_dac)
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###
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data_width = 2+2*3*bpc_dac
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fifo = AsyncFIFO(data_width, 512)
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self.add_submodule(fifo, {"write": "sys", "read": "vga"})
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fifo_in = self.dac.payload
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fifo_out = Record(dac_layout)
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self.comb += [
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self.dac.ack.eq(fifo.writable),
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fifo.we.eq(self.dac.stb),
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout),
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self.busy.eq(0)
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]
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pix_parity = Signal()
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self.sync.vga += [
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pix_parity.eq(~pix_parity),
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self.vga_hsync_n.eq(~fifo_out.hsync),
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self.vga_vsync_n.eq(~fifo_out.vsync),
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If(pix_parity,
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self.vga_r.eq(fifo_out.p1.r),
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self.vga_g.eq(fifo_out.p1.g),
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self.vga_b.eq(fifo_out.p1.b)
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).Else(
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self.vga_r.eq(fifo_out.p0.r),
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self.vga_g.eq(fifo_out.p0.g),
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self.vga_b.eq(fifo_out.p0.b)
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)
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]
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self.comb += fifo.re.eq(pix_parity)
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def sim_fifo_gen():
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while True:
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t = Token("dac")
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yield t
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print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
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+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
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