Florent Kermarrec 76d3a77cf3 interconnect/csr_bus: Fix build with custom get_csrs/get_constants from cores.		2022-10-21 22:01:34 +02:00
..
build	build/sim/platform: Remove add_csr calls no longer required.	2022-10-21 08:43:51 +02:00
compat
gen	fhdl/verilog: Switch tab to 4 spaces.	2022-10-21 19:49:04 +02:00
soc	interconnect/csr_bus: Fix build with custom get_csrs/get_constants from cores.	2022-10-21 22:01:34 +02:00
tools	tools/litex_read_verilog: Add proc step before exporting to .json since now seems to be required for some verilog designs.	2022-10-19 15:29:00 +02:00
__init__.py