litex/litex
Chris Ballance 782711e5a9 bios/sdram: make read leveling robust for KUS SDRAM
Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
2018-01-12 19:23:08 +01:00
..
boards Merge pull request #44 from felixheld/nexys_video-dram-fix 2018-01-12 14:08:03 +11:00
build build/xilinx/vivado: only generate constraints that are not empty 2018-01-08 17:03:19 +01:00
gen fhdl/tracer: Import Python 3.5/3.6 version guards from Migen. 2017-12-29 19:56:52 -05:00
soc bios/sdram: make read leveling robust for KUS SDRAM 2018-01-12 19:23:08 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00