84 lines
2.8 KiB
Python
84 lines
2.8 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.bus import wishbone
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_count_width = 11
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class MiniMAC(Module, AutoCSR):
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def __init__(self, pads):
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# CPU interface
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self._phy_reset = CSRStorage(reset=1)
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self._rx_count_0 = CSRStatus(_count_width)
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self._rx_count_1 = CSRStatus(_count_width)
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self._tx_count = CSRStorage(_count_width, write_from_dev=True)
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self._tx_start = CSR()
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self.submodules.ev = EventManager()
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self.ev.rx0 = EventSourcePulse()
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self.ev.rx1 = EventSourcePulse()
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self.ev.tx = EventSourcePulse()
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self.ev.finalize()
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self.membus = wishbone.Interface()
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###
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init = Signal(reset=1)
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self.sync += init.eq(0)
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rx_ready_0 = Signal()
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rx_ready_1 = Signal()
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rx_pending_0 = self.ev.rx0.pending
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rx_pending_1 = self.ev.rx1.pending
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rx_pending_0_r = Signal()
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rx_pending_1_r = Signal()
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self.comb += [
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pads.rst_n.eq(~self._phy_reset.storage),
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rx_ready_0.eq(init | (rx_pending_0_r & ~rx_pending_0)),
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rx_ready_1.eq(init | (rx_pending_1_r & ~rx_pending_1)),
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self._tx_count.dat_w.eq(0),
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self._tx_count.we.eq(self.ev.tx.trigger)
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]
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self.sync += [
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rx_pending_0_r.eq(rx_pending_0),
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rx_pending_1_r.eq(rx_pending_1)
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]
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self.specials += Instance("minimac3",
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Instance.Input("sys_clk", ClockSignal()),
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Instance.Input("sys_rst", ResetSignal()),
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Instance.Output("rx_done_0", self.ev.rx0.trigger),
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Instance.Output("rx_count_0", self._rx_count_0.status),
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Instance.Output("rx_done_1", self.ev.rx1.trigger),
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Instance.Output("rx_count_1", self._rx_count_1.status),
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Instance.Input("rx_ready_0", rx_ready_0),
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Instance.Input("rx_ready_1", rx_ready_1),
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Instance.Input("tx_start", self._tx_start.re),
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Instance.Input("tx_count", self._tx_count.storage),
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Instance.Output("tx_done", self.ev.tx.trigger),
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Instance.Input("wb_adr_i", self.membus.adr),
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Instance.Input("wb_dat_i", self.membus.dat_w),
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Instance.Input("wb_sel_i", self.membus.sel),
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Instance.Input("wb_stb_i", self.membus.stb),
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Instance.Input("wb_cyc_i", self.membus.cyc),
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Instance.Input("wb_we_i", self.membus.we),
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Instance.Output("wb_dat_o", self.membus.dat_r),
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Instance.Output("wb_ack_o", self.membus.ack),
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Instance.Input("phy_tx_clk", ClockSignal("eth_tx")),
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Instance.Output("phy_tx_data", pads.tx_data),
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Instance.Output("phy_tx_en", pads.tx_en),
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Instance.Output("phy_tx_er", pads.tx_er),
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Instance.Input("phy_rx_clk", ClockSignal("eth_rx")),
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Instance.Input("phy_rx_data", pads.rx_data),
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Instance.Input("phy_dv", pads.dv),
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Instance.Input("phy_rx_er", pads.rx_er),
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Instance.Input("phy_col", pads.col),
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Instance.Input("phy_crs", pads.crs))
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