89 lines
2.1 KiB
Python
89 lines
2.1 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.misc import optree
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control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
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class Encoder(Module):
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def __init__(self):
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self.d = Signal(8)
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self.c = Signal(2)
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self.de = Signal()
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self.output = Signal(10)
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###
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# stage 1 - count number of 1s in data
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d = Signal(8)
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n1d = Signal(max=9)
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self.sync += [
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n1d.eq(optree("+", [self.d[i] for i in range(8)])),
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d.eq(self.d)
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]
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# stage 2 - add 9th bit
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q_m = Signal(9)
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q_m8_n = Signal()
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self.comb += q_m8_n.eq((n1d > 4) | ((n1d == 4) & ~d[0]))
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for i in range(8):
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if i:
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curval = curval ^ d[i] ^ q_m8_n
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else:
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curval = d[0]
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self.sync += q_m[i].eq(curval)
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self.sync += q_m[8].eq(~q_m8_n)
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# stage 3 - count number of 1s and 0s in q_m[:8]
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q_m_r = Signal(9)
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n0q_m = Signal(max=9)
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n1q_m = Signal(max=9)
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self.sync += [
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n0q_m.eq(optree("+", [~q_m[i] for i in range(8)])),
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n1q_m.eq(optree("+", [q_m[i] for i in range(8)])),
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q_m_r.eq(q_m)
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]
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# stage 4 - final encoding
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cnt = Signal((5, True))
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s_c = self.c
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s_de = self.de
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for p in range(3):
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new_c = Signal(2)
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new_de = Signal()
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self.sync += new_c.eq(s_c), new_de.eq(s_de)
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s_c, s_de = new_c, new_de
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self.sync += If(s_de,
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If((cnt == 0) | (n1q_m == n0q_m),
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self.output[9].eq(~q_m_r[8]),
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self.output[8].eq(q_m_r[8]),
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If(q_m_r[8],
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self.output[:8].eq(q_m_r[:8]),
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cnt.eq(cnt + n1q_m - n0q_m)
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).Else(
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self.output[:8].eq(~q_m_r[:8]),
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cnt.eq(cnt + n0q_m - n1q_m)
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)
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).Else(
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If((~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m)),
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self.output[9].eq(1),
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self.output[8].eq(q_m_r[8]),
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self.output[:8].eq(~q_m_r[:8]),
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cnt.eq(cnt + Cat(0, q_m_r[8]) + n0q_m - n1q_m)
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).Else(
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self.output[9].eq(0),
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self.output[8].eq(q_m_r[8]),
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self.output[:8].eq(q_m_r[:8]),
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cnt.eq(cnt - Cat(0, ~q_m_r[8]) + n1q_m - n0q_m)
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)
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)
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).Else(
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self.output.eq(Array(control_tokens)[s_c]),
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cnt.eq(0)
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)
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if __name__ == "__main__":
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from migen.fhdl import verilog
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print(verilog.convert(Encoder()))
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