24 lines
471 B
Python
24 lines
471 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self):
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dx = 5
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dy = 5
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x = Signal(max=dx)
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y = Signal(max=dy)
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out = Signal()
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my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
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self.comb += out.eq(my_2d_array[x][y])
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we = Signal()
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inp = Signal()
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self.sync += If(we,
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my_2d_array[x][y].eq(inp)
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)
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print(verilog.convert(Example()))
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