30 lines
761 B
Python
30 lines
761 B
Python
from migen.fhdl.structure import *
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from migen.bus import wishbone
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class SRAM:
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def __init__(self, depth):
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self.bus = wishbone.Interface()
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self.depth = depth
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def get_fragment(self):
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# memory
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mem = Memory(32, self.depth)
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port = mem.get_port(write_capable=True, we_granularity=8)
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# generate write enable signal
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comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(4)]
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# address and data
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comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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port.dat_w.eq(self.bus.dat_w),
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self.bus.dat_r.eq(port.dat_r)
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]
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# generate ack
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sync = [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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self.bus.ack.eq(1)
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)
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]
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return Fragment(comb, sync, memories=[mem])
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