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litex/mibuild/xilinx
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Florent Kermarrec 7afa3d61d9 mibuild/xilinx: Xilinx's FPGAs do not necessary share the same primitives: add xilinx_s7_special_overrides and specific XilinxDDROutputS7 implementation 
Fix DDROutput implementation on spartan6 (tested with LiteETH's GMII phy)
 		2015-07-02 09:42:12 +02:00
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__init__.py platforms/kc705: add iMPACT programmer 2015-03-29 12:15:39 +02:00
common.py mibuild/xilinx: Xilinx's FPGAs do not necessary share the same primitives: add xilinx_s7_special_overrides and specific XilinxDDROutputS7 implementation 2015-07-02 09:42:12 +02:00
ise.py mibuild/xilinx/ise: fix source and set source to False by default on Windows (tools supposed to be in the PATH) 2015-06-19 00:52:39 +02:00
platform.py mibuild/xilinx: Xilinx's FPGAs do not necessary share the same primitives: add xilinx_s7_special_overrides and specific XilinxDDROutputS7 implementation 2015-07-02 09:42:12 +02:00
programmer.py global: pep8 (E401) 2015-04-13 20:54:19 +02:00
vivado.py mibuild: add support for libraries, move .replace("\\", "/") to generic_platform.py and execute it only on Windows machines. 2015-04-17 00:11:31 +02:00