160 lines
5.3 KiB
Plaintext
160 lines
5.3 KiB
Plaintext
__ _ __ _______ _________
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/ / (_) /____ / __/ _ /_ __/ _ |
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/ /__/ / __/ -_)\ \/ __ |/ / / __ |
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/____/_/\__/\__/___/_/ |_/_/ /_/ |_|
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Copyright 2014-2015 HKU
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A small footprint and configurable SATA core
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developed for HKU by M-Labs Ltd & EnjoyDigital
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[> Intro
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---------
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LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
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LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
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FPGA IP cores by providing simple, elegant and efficient implementations of
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components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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The synthetizable BIST can be used as a starting point to integrate SATA in
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your own SoC.
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LiteSATA uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteSATA can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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PHY:
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- OOB, COMWAKE, COMINIT
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- ALIGN inserter/remover and bytes alignment on K28.5
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- 8B/10B encoding/decoding in transceiver
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- Errors detection and reporting
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- 32 bits interface
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- 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
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Core:
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Link:
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- CONT inserter/remover
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- Scrambling/Descrambling of data
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- CRC inserter/checker
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- HOLD insertion/detection
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- Errors detection and reporting
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Transport/Command:
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- Easy to use user interfaces (Can be used with or without CPU)
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- 48 bits sector addressing
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- 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
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- Errors detection and reporting
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Frontend:
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- Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
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- Ports arbitration transparent to the user
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- Synthetizable BIST
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[> Possibles improvements
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-------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add NCQ support
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- add AES hardware encryption
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- add on-the-flow compression/decompression
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- add support for Altera PHYs.
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- add support for Lattice PHYs.
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- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
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supported)
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- add Zynq Linux drivers.
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- ... See below Support and Consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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[> Getting started
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------------------
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1. Install Python3 and Xilinx's Vivado software
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2. Obtain Migen and install it:
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git clone https://github.com/m-labs/migen
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cd migen
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python3 setup.py install
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cd ..
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3. Obtain Miscope and install it:
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git clone https://github.com/m-labs/miscope
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cd miscope
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python3 setup.py install
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cd ..
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4. Obtain MiSoC:
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git clone https://github.com/m-labs/misoc --recursive
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XXX add setup.py to MiSoC for external use of misoclib?
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5. Obtain LiteSATA
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git clone https://github.com/enjoy-digital/litesata
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6. Build and load BIST design (only for KC705 for now):
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python3 make.py all
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7. Test design (only for KC705 for now):
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go to ./test directory and run:
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python3 bist.py
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8. If you only want to build the core and use it with your
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regular design flow:
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python3 make.py -t core build-core
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[> Simulations:
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Simulations are available in ./lib/sata/test:
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- crc_tb
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- scrambler_tb
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- phy_datapath_tb
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- link_tb
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- command_tb
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- bist_tb
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hdd.py is a simplified HDD model implementing all SATA layers.
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To run a simulation, move to ./lib/sata/test and run:
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make simulation_name
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[> Tests :
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A synthetizable BIST is provided and can be controlled with ./test/bist.py
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By using Miscope and the provided ./test/test_link.py example you are able to
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visualize the internal logic of the design and even inject the captured data in
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the HDD model!
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[> License
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-----------
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LiteSATA is released under the very permissive two-clause BSD license. Under the
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terms of this license, you are authorized to use LiteSATA for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteSATA
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- cite LiteSATA in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteSATA.
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[> Support and Consulting
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--------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteSATA is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteSATA or if you are already a happy user
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and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr
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