31 lines
896 B
Python
31 lines
896 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl import verilog
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from migen.genlib.cdc import MultiReg
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from migen.bank import description, csrgen
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from migen.bank.description import READ_ONLY, WRITE_ONLY
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class Example(Module):
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def __init__(self, ninputs=32, noutputs=32):
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r_o = description.RegisterField(noutputs, atomic_write=True)
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r_i = description.RegisterField(ninputs, READ_ONLY, WRITE_ONLY)
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self.submodules.bank = csrgen.Bank([r_o, r_i])
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self.gpio_in = Signal(ninputs)
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self.gpio_out = Signal(ninputs)
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###
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gpio_in_s = Signal(ninputs)
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self.specials += MultiReg(self.gpio_in, "ext", gpio_in_s, "sys")
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self.comb += [
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r_i.field.w.eq(gpio_in_s),
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self.gpio_out.eq(r_o.field.r)
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]
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example = Example()
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i = example.bank.bus
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v = verilog.convert(example, {i.dat_r, i.adr, i.we, i.dat_w,
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example.gpio_in, example.gpio_out})
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print(v)
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