Florent Kermarrec 7bc34a9bc7 integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). ... When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.		2020-01-29 08:31:41 +01:00
..
cores	cores/clock/create_clkout: rename clk_ce to ce, improve error reporting	2020-01-24 09:10:31 +01:00
integration	integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM).	2020-01-29 08:31:41 +01:00
interconnect	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
software	software/bios: revert M-Labs MiSoC copyright.	2020-01-27 13:12:37 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00