204 lines
4.1 KiB
Verilog
204 lines
4.1 KiB
Verilog
/*
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* Milkymist-NG SoC
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* Copyright (C) 2007, 2008, 2009, 2010, 2011, 2012 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module m1crg #(
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parameter in_period = 0.0,
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parameter f_mult = 0,
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parameter f_div = 0,
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parameter clk2x_period = (in_period*f_div)/(2.0*f_mult)
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) (
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input clkin,
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input trigger_reset,
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output sys_clk,
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output reg sys_rst,
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/* Reset off-chip devices */
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output ac97_rst_n,
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output videoin_rst_n,
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output flash_rst_n,
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/* DDR PHY clocks */
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output clk2x_270,
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output clk4x_wr,
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output clk4x_wr_strb,
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output clk4x_rd,
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output clk4x_rd_strb
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);
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/*
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* Reset
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*/
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reg [19:0] rst_debounce;
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always @(posedge sys_clk) begin
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if(trigger_reset)
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rst_debounce <= 20'hFFFFF;
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else if(rst_debounce != 20'd0)
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rst_debounce <= rst_debounce - 20'd1;
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sys_rst <= rst_debounce != 20'd0;
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end
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assign ac97_rst_n = ~sys_rst;
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assign videoin_rst_n = ~sys_rst;
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/*
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* We must release the Flash reset before the system reset
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* because the Flash needs some time to come out of reset
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* and the CPU begins fetching instructions from it
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* as soon as the system reset is released.
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* From datasheet, minimum reset pulse width is 100ns
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* and reset-to-read time is 150ns.
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*/
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reg [7:0] flash_rstcounter;
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always @(posedge sys_clk) begin
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if(trigger_reset)
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flash_rstcounter <= 8'd0;
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else if(~flash_rstcounter[7])
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flash_rstcounter <= flash_rstcounter + 8'd1;
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end
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assign flash_rst_n = flash_rstcounter[7];
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/*
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* Clock management. Inspired by the NWL reference design.
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*/
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wire sdr_clkin;
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wire clkdiv;
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IBUF #(
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.IOSTANDARD("DEFAULT")
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) clk2_iob (
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.I(clkin),
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.O(sdr_clkin)
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);
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BUFIO2 #(
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.DIVIDE(1),
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.DIVIDE_BYPASS("FALSE"),
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.I_INVERT("FALSE")
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) bufio2_inst2 (
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.I(sdr_clkin),
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.IOCLK(),
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.DIVCLK(clkdiv),
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.SERDESSTROBE()
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);
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wire pll_lckd;
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wire buf_pll_fb_out;
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wire pllout0;
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wire pllout1;
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wire pllout2;
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wire pllout3;
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PLL_ADV #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(4*f_mult),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(in_period),
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.CLKIN2_PERIOD(in_period),
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.CLKOUT0_DIVIDE(f_div),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(f_div),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(2*f_div),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(270.0),
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.CLKOUT3_DIVIDE(4*f_div),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_DIVIDE(7),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(7),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0.0),
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.COMPENSATION("INTERNAL"),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER(0.100),
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.CLK_FEEDBACK("CLKFBOUT"),
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.SIM_DEVICE("SPARTAN6")
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) pll (
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.CLKFBDCM(),
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.CLKFBOUT(buf_pll_fb_out),
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.CLKOUT0(pllout0), /* < x4 clock for writes */
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.CLKOUT1(pllout1), /* < x4 clock for reads */
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.CLKOUT2(pllout2), /* < x2 90 clock to generate memory clock, clock DQS and memory address and control signals. */
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.CLKOUT3(pllout3), /* < x1 clock for system and memory controller */
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUTDCM0(),
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.CLKOUTDCM1(),
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.CLKOUTDCM2(),
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.CLKOUTDCM3(),
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.CLKOUTDCM4(),
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.CLKOUTDCM5(),
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.DO(),
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.DRDY(),
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.LOCKED(pll_lckd),
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.CLKFBIN(buf_pll_fb_out),
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.CLKIN1(clkdiv),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(5'b00000),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'h0000),
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.DWE(1'b0),
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.RST(1'b0),
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.REL(1'b0)
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);
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BUFPLL #(
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.DIVIDE(4)
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) wr_bufpll (
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.PLLIN(pllout0),
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.GCLK(sys_clk),
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.LOCKED(pll_lckd),
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.IOCLK(clk4x_wr),
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.LOCK(),
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.SERDESSTROBE(clk4x_wr_strb)
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);
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BUFPLL #(
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.DIVIDE(4)
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) rd_bufpll (
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.PLLIN(pllout1),
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.GCLK(sys_clk),
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.LOCKED(pll_lckd),
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.IOCLK(clk4x_rd),
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.LOCK(),
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.SERDESSTROBE(clk4x_rd_strb)
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);
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BUFG bufg_x2_2(
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.I(pllout2),
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.O(clk2x_270)
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);
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BUFG bufg_x1(
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.I(pllout3),
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.O(sys_clk)
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);
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endmodule
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