litex/litex/soc
enjoy-digital 7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux
Rework booting Linux on VexRiscv
2019-07-22 11:44:20 +02:00
..
cores cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) 2019-07-22 10:28:03 +02:00
integration Merge pull request #216 from antmicro/booting_vexriscv_linux 2019-07-22 11:44:20 +02:00
interconnect soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs 2019-07-08 10:20:51 +02:00
software bios/boot: rework netboot/flashboot for VexRiscv in linux variant 2019-07-15 16:02:58 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00