litex

History

enjoy-digital 8303e462ec Merge pull request #1224 from fjullien/fix_add_sources platform: fix add_sources		2022-02-24 22:29:18 +01:00
..
core	sim: allow custom modules to be in custom path	2022-01-09 21:15:11 +01:00
verilog	litex: adding oddr/iddr/ddrtristate simulation models	2021-09-01 10:25:21 +02:00
README	litex/build/sim: add README	2017-06-28 16:55:32 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
common.py	fix: missing colon syntax error	2021-09-07 11:21:41 +01:00
config.py	build: add SPDX License identifier and specify file is part of LiteX.	2020-08-23 15:14:45 +02:00
gtkwave.py	build/sim/gtkwave: automate handling of Endpoint and other stream primitives	2021-07-22 15:49:20 +02:00
platform.py	build/toolchains: Specify passed toolchain when unknown.	2022-01-26 11:56:22 +01:00
verilator.py	Merge pull request #1224 from fjullien/fix_add_sources	2022-02-24 22:29:18 +01:00

README

LiteX Sim is a contribution from LambdaConcept and provides
a modular SoC simulation environment.

The contribution from LambdaConcept is a major rework/refactoring
of the original simulation environnment PoC that was hacky and not
modular.

LiteX Sim is Copyright (c) 2017 Pierre-Olivier Vauboin <po@lambdaconcept.com>
                           2017 Ramtin Amin <ramtin@lambdaconcept.com>

Original PoC is Copyright (c) 2015-2016 Florent Kermarrec <florent@enjoy-digital.fr>