282 lines
14 KiB
Python
282 lines
14 KiB
Python
#
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# This file is part of LiteHyperBus
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#
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# Copyright (c) 2019-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.cores.hyperbus import HyperRAM
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def c2bool(c):
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return {"-": 1, "_": 0}[c]
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class Pads: pass
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class HyperRamPads:
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def __init__(self, dw=8):
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self.clk = Signal()
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self.cs_n = Signal()
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self.dq = Record([("oe", 1), ("o", dw), ("i", dw)])
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self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)])
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class TestHyperBus(unittest.TestCase):
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def test_hyperram_syntax(self):
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pads = Record([("clk", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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pads = Record([("clk_p", 1), ("clk_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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def test_hyperram_write_latency_5_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________------"
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dq_oe = "__------------____________________________________--------______"
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dq_o = "002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________--------______"
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rwds_o = "____________________________________________________----________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_6_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________________------"
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dq_oe = "__------------____________________________________________--------______"
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dq_o = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________________--------______"
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rwds_o = "____________________________________________________________----________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_7_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________________________------"
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dq_oe = "__------------____________________________________________________--------______"
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dq_o = "002000048d00000000000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________________________________--------______"
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rwds_o = "____________________________________________________________________----________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_7_1x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--____________________________________________------"
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dq_oe = "__------------________________________--------______"
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dq_o = "002000048d0000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________--------______"
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rwds_o = "________________________________________----________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="variable")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_5_2x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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dat = yield from dut.bus.read(0x1235)
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self.assertEqual(dat, 0xcafefade)
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
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cs_n = "--________________________________________________________________________"
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dq_oe = "__------------____________________________________________________________"
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dq_o = "00a000048d0000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "00000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "__________________________________________________________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_6_2x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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dat = yield from dut.bus.read(0x1235)
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self.assertEqual(dat, 0xcafefade)
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
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cs_n = "--________________________________________________________________________________"
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dq_oe = "__------------____________________________________________________________________"
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dq_o = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "__________________________________________________________________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_7_2x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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dat = yield from dut.bus.read(0x1235)
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self.assertEqual(dat, 0xcafefade)
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
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cs_n = "--________________________________________________________________________________________"
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dq_oe = "__------------____________________________________________________________________________"
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dq_o = "00a000048d00000000000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "000000000000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "__________________________________________________________________________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_7_1x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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dat = yield from dut.bus.read(0x1235)
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self.assertEqual(dat, 0xcafefade)
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def hyperram_gen(dut):
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clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
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cs_n = "--____________________________________________________________"
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dq_oe = "__------------________________________________________________"
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dq_o = "00a000048d0000000000000000000000000000000000000000000000000000"
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dq_i = "00000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "______________________________________________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="variable")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_reg_write(self):
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def fpga_gen(dut):
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yield dut.reg_addr.eq(2)
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yield dut.reg_write_data.eq(0x1234)
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yield
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yield dut.reg_write.eq(1)
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yield
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yield dut.reg_write.eq(0)
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for i in range(128):
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yield
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def hyperram_gen(dut):
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clk = "___--__--__--__--___________"
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cs_n = "--________________----------"
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dq_oe = "__----------------__________"
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dq_o = "0060000100000012340000000000"
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rwds_oe = "____________________________"
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rwds_o = "____________________________"
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for i in range(3):
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), with_csr=False)
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") |