154 lines
3.8 KiB
Python
154 lines
3.8 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.misc import chooser
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from migen.actorlib.fifo import AsyncFIFO
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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class K7SATAPHYDatapathRX(Module):
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def __init__(self):
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self.sink = Sink([("data", 16), ("charisk", 2)])
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self.source = Source([("data", 32), ("charisk", 4)])
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###
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# bytes alignment
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# shift register
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data_sr = Signal(32+8)
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charisk_sr = Signal(4+1)
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data_sr_d = Signal(32+8)
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charisk_sr_d = Signal(4+1)
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self.comb += [
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data_sr.eq(Cat(self.sink.data, data_sr_d)),
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charisk_sr.eq(Cat(self.sink.charisk, charisk_sr_d))
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]
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self.sync.sata_rx += [
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data_sr_d.eq(data_sr),
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charisk_sr_d.eq(charisk_sr)
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]
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# alignment
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alignment = Signal()
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valid = Signal()
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self.sync.sata_rx += [
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If(self.sink.charisk !=0,
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alignment.eq(self.sink.charisk[1]),
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valid.eq(0)
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).Else(
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valid.eq(~valid)
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)
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]
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# 16 to 32
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data = Signal(32)
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charisk = Signal(4)
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self.comb += [
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If(~alignment,
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data.eq(data_sr[0:32]),
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charisk.eq(charisk_sr[0:4])
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).Else(
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data.eq(data_sr[8:40]),
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charisk.eq(charisk_sr[1:5])
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)
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]
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# clock domain crossing
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# (SATA3) 300MHz sata_rx clk to sys_clk
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# (SATA2) 150MHz sata_rx clk to sys_clk
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# (SATA1) 75MHz sata_rx clk to sys_clk
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# requirements:
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# due to the convertion ratio of 2, sys_clk need to be > sata_rx/2
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# source destination is always able to accept data (ack always 1)
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fifo = AsyncFIFO([("data", 32), ("charisk", 4)], 16)
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self.submodules.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
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self.comb += [
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fifo.sink.stb.eq(valid),
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fifo.sink.data.eq(data),
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fifo.sink.charisk.eq(charisk),
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]
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self.comb += Record.connect(fifo.source, self.source)
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class K7SATAPHYDatapathTX(Module):
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def __init__(self):
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self.sink = Sink([("data", 32), ("charisk", 4)])
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self.source = Source([("data", 16), ("charisk", 2)])
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###
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# clock domain crossing
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# (SATA3) sys_clk to 300MHz sata_tx clk
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# (SATA2) sys_clk to 150MHz sata_tx clk
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# (SATA1) sys_clk to 75MHz sata_tx clk
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# requirements:
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# source destination is always able to accept data (ack always 1)
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fifo = AsyncFIFO([("data", 32), ("charisk", 4)], 16)
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self.submodules.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
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self.comb += Record.connect(self.sink, fifo.sink)
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# 32 to 16
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mux = Signal()
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last = Signal()
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self.comb += [
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last.eq(mux == 1),
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self.source.stb.eq(fifo.source.stb),
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fifo.source.ack.eq(last),
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]
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self.sync.sata_tx += [
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If(self.source.stb,
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If(last,
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mux.eq(0)
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).Else(
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mux.eq(mux + 1)
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)
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)
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]
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self.comb += [
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chooser(fifo.source.data, mux, self.source.data),
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chooser(fifo.source.charisk, mux, self.source.charisk)
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]
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class K7SATAPHYDatapath(Module):
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def __init__(self, gtx, ctrl):
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self.sink = Sink([("data", 32), ("charisk", 4)])
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self.source = Source([("data", 32), ("charisk", 4)])
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###
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# change data width & cross domain crossing
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rx = K7SATAPHYDatapathRX()
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tx = K7SATAPHYDatapathTX()
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self.submodules += rx, tx
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self.comb += [
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rx.sink.data.eq(gtx.rxdata),
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rx.sink.charisk.eq(gtx.rxcharisk),
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gtx.txdata.eq(tx.source.data),
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gtx.txcharisk.eq(tx.source.charisk),
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]
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# user / ctrl mux
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self.comb += [
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# user
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If(ctrl.ready,
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tx.sink.stb.eq(self.sink.stb),
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tx.sink.data.eq(self.sink.data),
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tx.sink.charisk.eq(self.sink.charisk),
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self.sink.ack.eq(tx.sink.ack),
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self.source.stb.eq(rx.source.stb),
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self.source.data.eq(rx.source.data),
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self.source.charisk.eq(rx.source.charisk),
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rx.source.ack.eq(1),
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# ctrl
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).Else(
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tx.sink.stb.eq(ctrl.source.stb),
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tx.sink.data.eq(ctrl.source.data),
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tx.sink.charisk.eq(ctrl.source.charisk),
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ctrl.sink.stb.eq(rx.source.stb),
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ctrl.sink.data.eq(rx.source.data),
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rx.source.ack.eq(1),
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)
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]
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