286 lines
7.1 KiB
Python
286 lines
7.1 KiB
Python
from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migen.corelogic.misc import optree
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from migen.corelogic.fsm import *
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class Storage:
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#
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# Definition
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#
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def __init__(self, width, depth):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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# Control
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self.rst = Signal()
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self.start = Signal()
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self.offset = Signal(self.depth_width)
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self.size = Signal(self.depth_width)
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self.done = Signal()
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# Push Path
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self.push_stb = Signal()
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self.push_dat = Signal(self.width)
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self._push_ptr = Signal(self.depth_width)
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self._push_ptr_stop = Signal(self.depth_width)
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# Pull Path
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self.pull_stb = Signal()
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self.pull_dat = Signal(self.width)
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self._pull_ptr = Signal(self.depth_width)
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# Memory
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self._mem = Memory(self.width, self.depth)
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self._push_port = self._mem.get_port(write_capable=True)
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self._pull_port = self._mem.get_port(has_re=True)
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def get_fragment(self):
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comb = [
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self._push_port.adr.eq(self._push_ptr),
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self._push_port.we.eq(self.push_stb),
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self._push_port.dat_w.eq(self.push_dat),
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self._pull_port.adr.eq(self._pull_ptr),
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self._pull_port.re.eq(self.pull_stb),
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self.pull_dat.eq(self._pull_port.dat_r)
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]
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size_minus_offset = Signal(self.depth_width)
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comb += [size_minus_offset.eq(self.size-self.offset)]
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idle_rising = Signal()
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idle_ongoing = Signal()
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active_rising = Signal()
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active_ongoing = Signal()
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# FSM
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fsm = FSM("IDLE", "ACTIVE")
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# Idle
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fsm.act(fsm.IDLE,
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If(self.start,
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fsm.next_state(fsm.ACTIVE),
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active_rising.eq(1)
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),
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idle_ongoing.eq(1)
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)
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# Active
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fsm.act(fsm.ACTIVE,
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If(self.done | self.rst,
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fsm.next_state(fsm.IDLE),
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idle_rising.eq(1)
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),
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active_ongoing.eq(1)
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)
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sync =[
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If(active_rising,
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self._push_ptr_stop.eq(self._push_ptr + self.size - self.offset),
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self._pull_ptr.eq(self._push_ptr-self.offset-1)
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).Else(
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If(self.pull_stb, self._pull_ptr.eq(self._pull_ptr+1))
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),
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If(self.push_stb, self._push_ptr.eq(self._push_ptr+1)),
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]
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comb +=[self.done.eq((self._push_ptr == self._push_ptr_stop) & active_ongoing)]
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return Fragment(comb, sync, memories=[self._mem])
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class Sequencer:
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#
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# Definition
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#
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def __init__(self,depth):
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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# Controller interface
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self.ctl_rst = Signal()
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self.ctl_offset = Signal(self.depth_width)
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self.ctl_size = Signal(self.depth_width)
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self.ctl_arm = Signal()
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self.ctl_done = Signal()
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self._ctl_arm_d = Signal()
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# Trigger interface
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self.hit = Signal()
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# Recorder interface
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self.rec_offset = Signal(self.depth_width)
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self.rec_size = Signal(self.depth_width)
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self.rec_start = Signal()
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self.rec_done = Signal()
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# Others
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self.enable = Signal()
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def get_fragment(self):
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idle_rising = Signal()
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idle_ongoing = Signal()
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active_rising = Signal()
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active_ongoing = Signal()
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# FSM
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fsm = FSM("IDLE", "ACTIVE")
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# Idle
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fsm.act(fsm.IDLE,
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If(self.ctl_arm,
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fsm.next_state(fsm.ACTIVE),
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active_rising.eq(1)
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),
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idle_ongoing.eq(1)
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)
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# Active
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fsm.act(fsm.ACTIVE,
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If(self.rec_done,
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fsm.next_state(fsm.IDLE),
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idle_rising.eq(1)
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),
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active_ongoing.eq(1)
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)
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comb =[self.enable.eq(active_ongoing)]
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# trig_hit rising_edge
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_hit_d = Signal()
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_hit_rising = Signal()
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sync =[_hit_d.eq(self.hit)]
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comb +=[_hit_rising.eq(self.hit & ~_hit_d)]
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# connexion
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comb = [
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self.rec_offset.eq(self.ctl_offset),
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self.rec_size.eq(self.ctl_size),
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self.rec_start.eq(self.enable & _hit_rising),
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self.ctl_done.eq(~self.enable)
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]
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return Fragment(comb, sync)
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REC_RST_BASE = 0x00
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REC_ARM_BASE = 0x01
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REC_DONE_BASE = 0x02
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REC_SIZE_BASE = 0x03
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REC_OFFSET_BASE = 0x05
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REC_READ_BASE = 0x07
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REC_READ_DATA_BASE = 0x09
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class Recorder:
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#
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# Definition
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#
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def __init__(self, width, depth, address = 0x0000, interface = None):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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self.storage = Storage(self.width, self.depth)
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self.sequencer = Sequencer(self.depth)
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# csr interface
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self._rst = RegisterField("rst", reset=1)
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self._arm = RegisterField("arm", reset=0)
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self._done = RegisterField("done", reset=0, access_bus=READ_ONLY,
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access_dev=WRITE_ONLY)
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self._size = RegisterField("size", self.depth_width, reset=1)
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self._offset = RegisterField("offset", self.depth_width, reset=1)
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self._pull_stb = RegisterField("pull_stb", reset=0)
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self._pull_dat = RegisterField("pull_dat", self.width, reset=1,
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access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self.regs = [self._rst, self._arm, self._done, self._size, self._offset,
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self._pull_stb, self._pull_dat]
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self.bank = csrgen.Bank(self.regs, address=address)
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# set address / interface
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self.set_address(address)
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self.set_interface(interface)
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# trigger Interface
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self.hit = Signal()
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self.dat = Signal(self.width)
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def set_address(self, address):
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self.address = address
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self.bank = csrgen.Bank(self.regs,address=self.address)
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def set_interface(self, interface):
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self.interface = interface
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def get_fragment(self):
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_pull_stb_d = Signal()
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_pull_stb_rising = Signal()
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sync = [
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_pull_stb_d.eq(self._pull_stb.field.r),
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_pull_stb_rising.eq(self._pull_stb.field.r & ~_pull_stb_d)
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]
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# Bank <--> Storage / Sequencer
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comb = [
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self.sequencer.ctl_rst.eq(self._rst.field.r),
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self.storage.rst.eq(self._rst.field.r),
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self.sequencer.ctl_offset.eq(self._offset.field.r),
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self.sequencer.ctl_size.eq(self._size.field.r),
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self.sequencer.ctl_arm.eq(self._arm.field.r),
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self._done.field.w.eq(self.sequencer.ctl_done),
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self.storage.pull_stb.eq(_pull_stb_rising),
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self._pull_dat.field.w.eq(self.storage.pull_dat)
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]
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# Storage <--> Sequencer <--> Trigger
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comb += [
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self.storage.offset.eq(self.sequencer.rec_offset),
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self.storage.size.eq(self.sequencer.rec_size),
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self.storage.start.eq(self.sequencer.rec_start),
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self.sequencer.rec_done.eq(self.storage.done),
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self.sequencer.hit.eq(self.hit),
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self.storage.push_stb.eq(self.sequencer.enable),
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self.storage.push_dat.eq(self.dat)
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]
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return self.bank.get_fragment() + Fragment(comb, sync) +\
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self.storage.get_fragment() + self.sequencer.get_fragment()
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#
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#Driver
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#
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def reset(self):
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self.interface.write(self.address + REC_RST_BASE, 1)
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self.interface.write(self.address + REC_RST_BASE, 0)
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def arm(self):
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self.interface.write(self.address + REC_ARM_BASE, 1)
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self.interface.write(self.address + REC_ARM_BASE, 0)
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def is_done(self):
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return self.interface.read(self.address + REC_DONE_BASE) == 1
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def size(self, dat):
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self.interface.write_n(self.address + REC_SIZE_BASE, dat, 16)
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def offset(self, dat):
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self.interface.write_n(self.address + REC_OFFSET_BASE, dat, 16)
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def read(self, size):
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r = []
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for i in range(size):
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self.interface.write(self.address + REC_READ_BASE, 1)
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self.interface.write(self.address + REC_READ_BASE, 0)
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r.append(self.interface.read_n(self.address + REC_READ_DATA_BASE, self.width))
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return r
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