326 lines
9.3 KiB
Python
326 lines
9.3 KiB
Python
from migen.fhdl.std import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import optree, chooser
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from migen.genlib.fsm import FSM, NextState
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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_layout = [
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("adr", 30, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self, data_width=32):
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Record.__init__(self, set_layout_parameters(_layout,
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data_width=data_width,
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sel_width=data_width//8))
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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class Arbiter(Module):
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def __init__(self, masters, target):
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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# mux master->slave signals
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(target, name).eq(choices[self.rr.grant])
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# connect slave->master signals
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for name, size, direction in _layout:
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if direction == DIR_S_TO_M:
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source = getattr(target, name)
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for i, m in enumerate(masters):
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dest = getattr(m, name)
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if name == "ack" or name == "err":
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self.comb += dest.eq(source & (self.rr.grant == i))
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else:
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self.comb += dest.eq(source)
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# connect bus requests to round-robin selector
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reqs = [m.cyc for m in masters]
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self.comb += self.rr.request.eq(Cat(*reqs))
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class Decoder(Module):
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# slaves is a list of pairs:
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# 0) function that takes the address signal and returns a FHDL expression
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# that evaluates to 1 when the slave is selected and 0 otherwise.
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# 1) wishbone.Slave reference.
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# register adds flip-flops after the address comparators. Improves timing,
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# but breaks Wishbone combinatorial feedback.
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def __init__(self, master, slaves, register=False):
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ns = len(slaves)
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slave_sel = Signal(ns)
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slave_sel_r = Signal(ns)
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# decode slave addresses
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self.comb += [slave_sel[i].eq(fun(master.adr))
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for i, (fun, bus) in enumerate(slaves)]
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if register:
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self.sync += slave_sel_r.eq(slave_sel)
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else:
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self.comb += slave_sel_r.eq(slave_sel)
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# connect master->slaves signals except cyc
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for slave in slaves:
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S and name != "cyc":
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self.comb += getattr(slave[1], name).eq(getattr(master, name))
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# combine cyc with slave selection signals
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self.comb += [slave[1].cyc.eq(master.cyc & slave_sel[i])
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for i, slave in enumerate(slaves)]
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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self.comb += [
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master.ack.eq(optree("|", [slave[1].ack for slave in slaves])),
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master.err.eq(optree("|", [slave[1].err for slave in slaves]))
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]
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# mux (1-hot) slave data return
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masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
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self.comb += master.dat_r.eq(optree("|", masked))
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class InterconnectShared(Module):
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def __init__(self, masters, slaves, register=False):
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shared = Interface()
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self.submodules += Arbiter(masters, shared)
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self.submodules += Decoder(shared, slaves, register)
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class Crossbar(Module):
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def __init__(self, masters, slaves, register=False):
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matches, busses = zip(*slaves)
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access = [[Interface() for j in slaves] for i in masters]
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# decode each master into its access row
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for row, master in zip(access, masters):
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row = list(zip(matches, row))
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self.submodules += Decoder(master, row, register)
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# arbitrate each access column onto its slave
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for column, bus in zip(zip(*access), busses):
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self.submodules += Arbiter(column, bus)
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class DownConverter(Module):
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# DownConverter splits Wishbone accesses of N bits in M accesses of L bits where:
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# N is the original data-width
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# L is the target data-width
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# M = N/L
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def __init__(self, dw_i, dw_o):
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self.wishbone_i = Interface(dw_i)
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self.wishbone_o = Interface(dw_o)
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self.ratio = dw_i//dw_o
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###
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rst = Signal()
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# generate internal write and read ack
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write_ack = Signal()
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read_ack = Signal()
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ack = Signal()
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self.comb += [
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ack.eq(self.wishbone_o.cyc & self.wishbone_o.stb & self.wishbone_o.ack),
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write_ack.eq(ack & self.wishbone_o.we),
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read_ack.eq(ack & ~self.wishbone_o.we)
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]
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# accesses counter logic
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cnt = Signal(max=self.ratio)
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self.sync += If(rst, cnt.eq(0)).Elif(ack, cnt.eq(cnt + 1))
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# read data path
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dat_r = Signal(dw_i)
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self.sync += If(ack, dat_r.eq(Cat(self.wishbone_o.dat_r, dat_r[:dw_i-dw_o])))
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# write data path
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dat_w = Signal(dw_i)
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self.comb += dat_w.eq(self.wishbone_i.dat_w)
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# errors generation
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err = Signal()
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self.sync += If(ack, err.eq(self.wishbone_o.err))
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# direct connection of wishbone_i --> wishbone_o signals
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for name, size, direction in self.wishbone_i.layout:
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if direction == DIR_M_TO_S and name not in ["adr", "dat_w"]:
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self.comb += getattr(self.wishbone_o, name).eq(getattr(self.wishbone_i, name))
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# adaptation of adr & dat signals
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self.comb += [
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self.wishbone_o.adr[0:flen(cnt)].eq(cnt),
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self.wishbone_o.adr[flen(cnt):].eq(self.wishbone_i.adr)
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]
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self.comb += chooser(dat_w, cnt, self.wishbone_o.dat_w, reverse=True)
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# fsm
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(write_ack,
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NextState("WRITE_ADAPT")
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),
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If(read_ack,
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NextState("READ_ADAPT")
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)
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)
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fsm.act("WRITE_ADAPT",
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If(write_ack & (cnt == self.ratio-1),
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NextState("IDLE"),
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rst.eq(1),
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self.wishbone_i.err.eq(err | self.wishbone_o.err),
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self.wishbone_i.ack.eq(1),
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)
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)
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master_i_dat_r = Signal(dw_i)
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self.comb += master_i_dat_r.eq(Cat(self.wishbone_o.dat_r, dat_r[:dw_i-dw_o]))
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fsm.act("READ_ADAPT",
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If(read_ack & (cnt == self.ratio-1),
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NextState("IDLE"),
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rst.eq(1),
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self.wishbone_i.err.eq(err | self.wishbone_o.err),
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self.wishbone_i.ack.eq(1),
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self.wishbone_i.dat_r.eq(master_i_dat_r)
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)
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)
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class Tap(Module):
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def __init__(self, bus, handler=print):
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self.bus = bus
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self.handler = handler
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def do_simulation(self, s):
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if s.rd(self.bus.ack):
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assert(s.rd(self.bus.cyc) and s.rd(self.bus.stb))
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if s.rd(self.bus.we):
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transaction = TWrite(s.rd(self.bus.adr),
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s.rd(self.bus.dat_w),
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s.rd(self.bus.sel))
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else:
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transaction = TRead(s.rd(self.bus.adr),
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s.rd(self.bus.dat_r))
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self.handler(transaction)
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class Initiator(Module):
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def __init__(self, generator, bus=None):
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self.generator = generator
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if bus is None:
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bus = Interface()
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self.bus = bus
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self.transaction_start = 0
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self.transaction = None
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self.done = False
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def do_simulation(self, s):
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if not self.done:
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if self.transaction is None or s.rd(self.bus.ack):
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if self.transaction is not None:
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self.transaction.latency = s.cycle_counter - self.transaction_start - 1
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if isinstance(self.transaction, TRead):
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self.transaction.data = s.rd(self.bus.dat_r)
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.done = True
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self.transaction = None
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if self.transaction is not None:
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self.transaction_start = s.cycle_counter
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s.wr(self.bus.cyc, 1)
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s.wr(self.bus.stb, 1)
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s.wr(self.bus.adr, self.transaction.address)
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if isinstance(self.transaction, TWrite):
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s.wr(self.bus.we, 1)
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s.wr(self.bus.sel, self.transaction.sel)
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s.wr(self.bus.dat_w, self.transaction.data)
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else:
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s.wr(self.bus.we, 0)
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else:
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s.wr(self.bus.cyc, 0)
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s.wr(self.bus.stb, 0)
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class TargetModel:
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def read(self, address):
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return 0
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def write(self, address, data, sel):
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pass
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def can_ack(self, bus):
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return True
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class Target(Module):
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def __init__(self, model, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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self.model = model
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def do_simulation(self, s):
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bus = Proxy(s, self.bus)
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if not bus.ack:
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if self.model.can_ack(bus) and bus.cyc and bus.stb:
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if bus.we:
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self.model.write(bus.adr, bus.dat_w, bus.sel)
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else:
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bus.dat_r = self.model.read(bus.adr)
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bus.ack = 1
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else:
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bus.ack = 0
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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bus_data_width = flen(self.bus.dat_r)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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mem = mem_or_size
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else:
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mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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if read_only is None:
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if hasattr(mem, "bus_read_only"):
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read_only = mem.bus_read_only
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else:
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read_only = False
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###
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# memory
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port = mem.get_port(write_capable=not read_only, we_granularity=8)
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self.specials += mem, port
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# generate write enable signal
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if not read_only:
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self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(4)]
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# address and data
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self.comb += [
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port.adr.eq(self.bus.adr[:flen(port.adr)]),
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self.bus.dat_r.eq(port.dat_r)
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]
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.dat_w),
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# generate ack
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self.sync += [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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]
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