Florent Kermarrec f3f9808d1f interconnect/stream: add PipeValid and PipeWait to cut timing paths.		2020-01-29 18:27:29 +01:00
..
__init__.py
test_axi.py	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
test_bitbang.py
test_code_8b10b.py
test_csr.py
test_ecc.py
test_gearbox.py
test_hyperbus.py
test_icap.py
test_packet.py
test_prbs.py
test_spi.py
test_stream.py	interconnect/stream: add PipeValid and PipeWait to cut timing paths.	2020-01-29 18:27:29 +01:00
test_targets.py	test/test_targets: limit max_sdram_size to 1GB	2020-01-17 13:24:45 +01:00