54 lines
2.3 KiB
Python
54 lines
2.3 KiB
Python
from migen import *
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from misoc.interconnect import dfi, lasmi_bus
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from misoc.cores.lasmicon.refresher import *
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from misoc.cores.lasmicon.bankmachine import *
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from misoc.cores.lasmicon.multiplexer import *
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class ControllerSettings:
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def __init__(self, req_queue_size=8, read_time=32, write_time=16, with_bandwidth=False):
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self.req_queue_size = req_queue_size
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self.read_time = read_time
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self.write_time = write_time
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self.with_bandwidth = with_bandwidth
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class LASMIcon(Module):
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def __init__(self, phy_settings, geom_settings, timing_settings,
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controller_settings=None):
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if controller_settings is None:
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controller_settings = ControllerSettings()
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if phy_settings.memtype in ["SDR"]:
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burst_length = phy_settings.nphases*1 # command multiplication*SDR
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elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
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burst_length = phy_settings.nphases*2 # command multiplication*DDR
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address_align = log2_int(burst_length)
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self.dfi = dfi.Interface(geom_settings.addressbits,
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geom_settings.bankbits,
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phy_settings.dfi_databits,
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phy_settings.nphases)
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self.lasmic = lasmi_bus.Interface(
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aw=geom_settings.rowbits + geom_settings.colbits - address_align,
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dw=phy_settings.dfi_databits*phy_settings.nphases,
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nbanks=2**geom_settings.bankbits,
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req_queue_size=controller_settings.req_queue_size,
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read_latency=phy_settings.read_latency+1,
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write_latency=phy_settings.write_latency+1)
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self.nrowbits = geom_settings.colbits - address_align
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###
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self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
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timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
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self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
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getattr(self.lasmic, "bank"+str(i)))
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for i in range(2**geom_settings.bankbits)]
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self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings,
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self.bank_machines, self.refresher,
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self.dfi, self.lasmic)
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def get_csrs(self):
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return self.multiplexer.get_csrs()
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