Gabriel Somlo 441042bef4 yosys_nextpnr_toolchain: add flow3 option to abc9 mode ... Add "flow3" option to abc9 mode. This runs FPGA mapping several times, producing a generally better mapping at the cost of increased runtime (see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md). Also, add a "--yosys-flow3" build option to both "trellis" and "oxide". Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>		2022-09-18 08:28:40 -04:00
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build	yosys_nextpnr_toolchain: add flow3 option to abc9 mode	2022-09-18 08:28:40 -04:00
compat	cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI).	2022-01-07 19:08:03 +01:00
gen	gen/fhdl/namer: Minor cleanup to ease readability.	2022-05-09 17:53:27 +02:00
soc	interconnect/axi/axi_full: Fix AXIUpConverter compilation.	2022-09-16 14:06:22 +02:00
tools	soc/builder: Propagate data_width to get_mem_data.	2022-09-12 16:46:20 +02:00
__init__.py	get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.	2021-09-28 16:27:13 +02:00