Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
litex/litesata
History
Florent Kermarrec 91bb531641 bist: add loops parameter for more precision in speed computation 2015-01-22 01:33:02 +01:00
..
core command: remove success/failed redundancy (keep failed) 2015-01-22 00:23:11 +01:00
frontend bist: add loops parameter for more precision in speed computation 2015-01-22 01:33:02 +01:00
phy add verilog backend to use the core with a "standard" flow 2015-01-19 20:38:48 +01:00
test command: remove success/failed redundancy (keep failed) 2015-01-22 00:23:11 +01:00
__init__.py add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00
common.py command: remove success/failed redundancy (keep failed) 2015-01-22 00:23:11 +01:00