Hans Baier 7dae0aa09b litex_term: support Intel/Altera nios2-terminal		2021-02-08 11:42:37 +07:00
..
build	Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow	2021-02-04 16:41:45 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	demo: more helpful usage message	2021-02-06 07:15:12 +07:00
tools	litex_term: support Intel/Altera nios2-terminal	2021-02-08 11:42:37 +07:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00