Gwenhael Goavec-Merou 87c26a30fd soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode		2020-08-06 16:45:39 +02:00
..
boards	arty: Change USB-uart and I2S Pmod configuration	2020-08-05 11:38:51 +02:00
build	build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API.	2020-08-04 15:49:53 +02:00
gen	litex/gen: remove io that has been replaced with litex/build/io (and should have been removed).	2020-07-07 08:14:42 +02:00
soc	soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode	2020-08-06 16:45:39 +02:00
tools	tools/litex_json2dts: add missing copyrights.	2020-08-04 16:38:02 +02:00
__init__.py	litex/__init__.py: remove retro-compat > 6 months old.	2020-04-30 21:31:58 +02:00