17 lines
509 B
Python
17 lines
509 B
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.genlib.fsm import FSM, NextState
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class Example(Module):
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def __init__(self):
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self.s = Signal()
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myfsm = FSM()
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self.submodules += myfsm
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myfsm.act("FOO", self.s.eq(1), NextState("BAR"))
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myfsm.act("BAR", self.s.eq(0), NextState("FOO"))
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self.entering_foo = myfsm.entering("FOO")
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self.leaving_bar = myfsm.leaving("BAR")
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example = Example()
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print(verilog.convert(example, {example.s, example.entering_foo, example.leaving_bar}))
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