156 lines
4.0 KiB
Python
156 lines
4.0 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
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from migen.genlib.record import layout_len, Record
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def _inc(signal, modulo):
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if modulo == 2**flen(signal):
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return signal.eq(signal + 1)
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else:
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return If(signal == (modulo - 1),
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signal.eq(0)
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).Else(
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signal.eq(signal + 1)
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)
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class _FIFOInterface:
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def __init__(self, width_or_layout, depth):
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self.we = Signal()
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self.writable = Signal() # not full
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self.re = Signal()
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self.readable = Signal() # not empty
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if isinstance(width_or_layout, list):
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self.din = Record(width_or_layout)
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self.dout = Record(width_or_layout)
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self.din_bits = self.din.raw_bits()
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self.dout_bits = self.dout.raw_bits()
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self.width = layout_len(width_or_layout)
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else:
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self.din = Signal(width_or_layout)
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self.dout = Signal(width_or_layout)
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self.din_bits = self.din
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self.dout_bits = self.dout
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self.width = width_or_layout
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class SyncFIFO(Module, _FIFOInterface):
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def __init__(self, width_or_layout, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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###
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do_write = Signal()
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do_read = Signal()
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self.comb += [
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do_write.eq(self.writable & self.we),
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do_read.eq(self.readable & self.re)
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]
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level = Signal(max=depth+1)
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produce = Signal(max=depth)
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consume = Signal(max=depth)
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storage = Memory(self.width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True)
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self.specials += wrport
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self.comb += [
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wrport.adr.eq(produce),
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wrport.dat_w.eq(self.din_bits),
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wrport.we.eq(do_write)
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]
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self.sync += If(do_write, _inc(produce, depth))
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rdport = storage.get_port(async_read=True)
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self.specials += rdport
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self.comb += [
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rdport.adr.eq(consume),
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self.dout_bits.eq(rdport.dat_r)
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]
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self.sync += If(do_read, _inc(consume, depth))
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self.sync += [
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If(do_write,
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If(~do_read, level.eq(level + 1))
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).Elif(do_read,
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level.eq(level - 1)
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)
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]
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self.comb += [
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self.writable.eq(level != depth),
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self.readable.eq(level != 0)
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]
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class AsyncFIFO(Module, _FIFOInterface):
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def __init__(self, width_or_layout, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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###
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depth_bits = log2_int(depth, True)
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produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
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consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
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self.submodules += produce, consume
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self.comb += [
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produce.ce.eq(self.writable & self.we),
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consume.ce.eq(self.readable & self.re)
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]
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produce_rdomain = Signal(depth_bits+1)
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self.specials += [
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NoRetiming(produce.q),
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MultiReg(produce.q, produce_rdomain, "read")
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]
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consume_wdomain = Signal(depth_bits+1)
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self.specials += [
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NoRetiming(consume.q),
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MultiReg(consume.q, consume_wdomain, "write")
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]
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self.comb += [
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self.writable.eq((produce.q[-1] == consume_wdomain[-1])
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| (produce.q[-2] == consume_wdomain[-2])
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| (produce.q[:-2] != consume_wdomain[:-2])),
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self.readable.eq(consume.q != produce_rdomain)
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]
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storage = Memory(self.width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True, clock_domain="write")
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self.specials += wrport
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self.comb += [
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wrport.adr.eq(produce.q_binary[:-1]),
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wrport.dat_w.eq(self.din_bits),
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wrport.we.eq(produce.ce)
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]
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rdport = storage.get_port(clock_domain="read")
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self.specials += rdport
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self.comb += [
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rdport.adr.eq(consume.q_next_binary[:-1]),
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self.dout_bits.eq(rdport.dat_r)
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]
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class _SyncFIFOTB(Module):
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def __init__(self):
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self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
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self.sync += [
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If(self.dut.we & self.dut.writable,
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self.dut.din.a.eq(self.dut.din.a + 1),
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self.dut.din.b.eq(self.dut.din.b + 2)
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)
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]
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def do_simulation(self, s):
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s.wr(self.dut.we, s.cycle_counter % 4 == 0)
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s.wr(self.dut.re, s.cycle_counter % 3 == 0)
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print("readable: {0} re: {1} data: {2}/{3}".format(s.rd(self.dut.readable),
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s.rd(self.dut.re),
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s.rd(self.dut.dout.a), s.rd(self.dut.dout.b)))
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def _main():
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from migen.sim.generic import Simulator
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Simulator(_SyncFIFOTB()).run(20)
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if __name__ == "__main__":
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_main()
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