87 lines
2.9 KiB
Python
87 lines
2.9 KiB
Python
from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank.description import *
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class Bank:
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def __init__(self, description, address=0, interface=None):
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self.description = description
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self.address = address
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if interface is None:
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interface = csr.Interface()
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self.interface = interface
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def get_fragment(self):
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comb = []
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sync = []
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sel = Signal()
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comb.append(sel.eq(self.interface.adr[9:] == Constant(self.address, BV(5))))
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desc_exp = expand_description(self.description, csr.data_width)
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nbits = bits_for(len(desc_exp)-1)
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# Bus writes
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bwcases = []
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for i, reg in enumerate(desc_exp):
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if isinstance(reg, RegisterRaw):
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comb.append(reg.r.eq(self.interface.dat_w[:reg.size]))
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comb.append(reg.re.eq(sel & \
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self.interface.we & \
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(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
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elif isinstance(reg, RegisterFields):
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bwra = [Constant(i, BV(nbits))]
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offset = 0
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for field in reg.fields:
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if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
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bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
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offset += field.size
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if len(bwra) > 1:
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bwcases.append(bwra)
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# commit atomic writes
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for field in reg.fields:
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if isinstance(field, FieldAlias) and field.commit_list:
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commit_instr = [hf.commit_to.eq(hf.storage) for hf in field.commit_list]
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sync.append(If(sel & self.interface.we & self.interface.adr[:nbits] == i, *commit_instr))
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else:
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raise TypeError
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if bwcases:
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sync.append(If(sel & self.interface.we, Case(self.interface.adr[:nbits], *bwcases)))
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# Bus reads
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brcases = []
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for i, reg in enumerate(desc_exp):
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if isinstance(reg, RegisterRaw):
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brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(reg.w)])
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elif isinstance(reg, RegisterFields):
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brs = []
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reg_readable = False
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for field in reg.fields:
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if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
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brs.append(field.storage)
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reg_readable = True
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else:
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brs.append(Constant(0, BV(field.size)))
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if reg_readable:
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brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(Cat(*brs))])
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else:
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raise TypeError
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if brcases:
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sync.append(self.interface.dat_r.eq(0))
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sync.append(If(sel, Case(self.interface.adr[:nbits], *brcases)))
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else:
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comb.append(self.interface.dat_r.eq(0))
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# Device access
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for reg in self.description:
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if isinstance(reg, RegisterFields):
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for field in reg.fields:
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if field.access_bus == READ_ONLY and field.access_dev == WRITE_ONLY:
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comb.append(field.storage.eq(field.w))
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else:
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if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
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comb.append(field.r.eq(field.storage))
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if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
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sync.append(If(field.we, field.storage.eq(field.w)))
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return Fragment(comb, sync)
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