42 lines
1.2 KiB
Python
42 lines
1.2 KiB
Python
# Copyright (C) 2012 Vermeer Manufacturing Co.
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# License: GPLv3 with additional permissions (see README).
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from migen.fhdl.structure import *
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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# Our simple counter, which increments at every cycle
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# and prints its current value in simulation.
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class Counter:
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def __init__(self):
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self.count = Signal(BV(4))
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# This function will be called at every cycle.
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def do_simulation(self, s):
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# Simply read the count signal and print it.
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# The output is:
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# Count: 0
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# Count: 1
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# Count: 2
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# ...
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print("Count: " + str(s.rd(self.count)))
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def get_fragment(self):
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# At each cycle, increase the value of the count signal.
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# We do it with convertible/synthesizable FHDL code.
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sync = [self.count.eq(self.count + 1)]
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# List our simulation function in the fragment.
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sim = [self.do_simulation]
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return Fragment(sync=sync, sim=sim)
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def main():
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dut = Counter()
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# Use the Icarus Verilog runner.
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# We do not specify a top-level object, and use the default.
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sim = Simulator(dut.get_fragment(), Runner())
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# Since we do not use sim.interrupt, limit the simulation
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# to some number of cycles.
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sim.run(20)
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main()
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