581 lines
15 KiB
Python
581 lines
15 KiB
Python
# This file is Copyright (c) 2014 Robert Jordens <jordens@gmail.com>
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# License: BSD
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import struct
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from collections import namedtuple
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.record import Record
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.fifo import SyncFIFO
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from migen.genlib.misc import optree
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from migen.actorlib.structuring import Cast, Pack, Unpack, pack_layout
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from migen.actorlib.sim import SimActor
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from migen.bus.transactions import TRead, TWrite
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from migen.flow.transactions import Token
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from migen.flow.actor import Source, Sink
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from migen.flow.network import DataFlowGraph, CompositeActor
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_eb_width = 32 # addr and data
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_eb_queue_len = 32
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_eb_magic = 0x4e6f
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_eb_ver = 1
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_eb_hdr = [
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("magic", 16),
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("ver", 4),
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("res1", 1),
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("no_response", 1),
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("probe_res", 1),
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("probe", 1),
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("addr_size", 4),
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("data_size", 4),
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][::-1] # big-endian
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_eb_rec_hdr = [
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("bca_cfg", 1),
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("rca_cfg", 1),
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("rd_fifo", 1),
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("res1", 1),
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("drop_cyc", 1),
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("wca_cfg", 1),
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("wr_fifo", 1),
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("res2", 1),
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("sel", 8),
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("wr_cnt", 8),
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("rd_cnt", 8),
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][::-1] # big-endian
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_eb_layout = [("data", _eb_width)]
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class Config(Module):
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def __init__(self, sdb_addr):
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self.errreg = Signal(8*8)
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mach = Signal(4*8, reset=0xd15e)
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macl = Signal(4*8, reset=0xa5edbeef)
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self.mac = Signal(6*8)
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self.comb += self.mac.eq(Cat(macl, mach))
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self.ip = Signal(4*8, reset=0xc0a80064)
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self.port = Signal(4*8, reset=0xebd0)
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self.bus = bus = wishbone.Interface()
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self.submodules.fifo = SyncFIFO(3, _eb_queue_len)
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read_mux = Array([self.errreg[32:], self.errreg[:32], 0,
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sdb_addr, mach, macl, self.ip, self.port])
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write_mux = Array([mach, macl, self.ip, self.port])[bus.adr - 4]
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self.dout = read_mux[self.fifo.dout]
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self.comb += [
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bus.ack.eq(bus.cyc & bus.stb),
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bus.dat_r.eq(read_mux[bus.adr[:3]]),
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]
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self.sync += [
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If(bus.cyc & bus.stb & bus.we & optree("|",
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[bus.adr[:3] == i for i in (4, 5, 6, 7)]),
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write_mux.eq(bus.dat_w),
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)]
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class WishboneMaster(Module):
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def __init__(self, timeout):
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self.bus = bus = wishbone.Interface()
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self.submodules.fifo = SyncFIFO(_eb_width + 1, _eb_queue_len)
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self.active = Signal()
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inflight = Signal(max=_eb_queue_len)
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queued = Signal(max=_eb_queue_len)
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self.sync += [
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inflight.eq(inflight + self.active - self.fifo.we),
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queued.eq(queued + self.active - self.fifo.re),
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]
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self.busy = Signal()
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self.full = Signal()
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self.comb += [
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self.busy.eq(inflight != 0),
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self.full.eq(queued == _eb_queue_len - 1),
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]
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kill_ack = Signal()
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time = Signal(max=timeout)
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self.comb += kill_ack.eq(time == timeout - 1)
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self.sync += [
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If(self.fifo.we | ~self.busy,
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time.eq(0),
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).Else(
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time.eq(time + 1),
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)]
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self.comb += [
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self.fifo.we.eq(bus.ack | bus.err | kill_ack),
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self.fifo.din.eq(Cat(bus.dat_r, ~bus.ack)),
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]
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self.errreg = Signal(64)
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self.sync += [
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If(self.fifo.re,
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self.errreg.eq(Cat(self.fifo.dout[-1], self.errreg)),
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)]
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class Transmit(Module):
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def __init__(self, pas, cfg, wbm, tag, tags):
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self.tx = Source(_eb_layout)
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data = Signal(_eb_width)
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re = Signal(4)
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self.tx_cyc = Signal()
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self.tx_skip = Signal()
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last_tx_cyc = Signal()
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last_tx_skip = Signal()
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readable = Signal()
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self.sync += [
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last_tx_cyc.eq(self.tx_cyc),
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last_tx_skip.eq(self.tx_skip),
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]
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self.comb += [
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readable.eq(Cat(tag.readable, pas.readable,
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cfg.fifo.readable, wbm.readable) & re == re),
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self.tx.stb.eq(readable & (re[1:] != 0)),
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self.tx.payload.data.eq(data),
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Case(tag.dout, {
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tags["PASS_TX"]: [re.eq(0b0011), data.eq(pas.dout)],
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tags["PASS_ON"]: [re.eq(0b0011), data.eq(pas.dout)],
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tags["CFG_REQ"]: [re.eq(0b0101), data.eq(cfg.dout)],
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tags["CFG_IGN"]: [re.eq(0b0111), data.eq(pas.dout)],
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tags["WBM_REQ"]: [re.eq(0b1001), data.eq(wbm.dout)],
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tags["WBM_IGN"]: [re.eq(0b1011), data.eq(pas.dout)],
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"default": [re.eq(0b0001)],
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}),
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If(readable & (self.tx.ack | (re[1:] == 0)),
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Cat(tag.re, pas.re, cfg.fifo.re, wbm.re).eq(re),
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),
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If(tag.readable,
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If(tag.dout == tags["PASS_TX"],
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self.tx_cyc.eq(1),
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self.tx_skip.eq(0),
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).Elif(tag.dout == tags["SKIP_TX"],
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self.tx_cyc.eq(0),
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self.tx_skip.eq(1),
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).Elif(tag.dout == tags["DROP_TX"],
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self.tx_cyc.eq(0),
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self.tx_skip.eq(0),
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).Else(
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self.tx_cyc.eq(last_tx_cyc),
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self.tx_skip.eq(last_tx_skip),
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),
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).Else(
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self.tx_cyc.eq(last_tx_cyc),
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self.tx_skip.eq(last_tx_skip),
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),
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]
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class Receive(Module):
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def __init__(self, pas, cfg, wbm, tag, tags):
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self.rx = Sink(_eb_layout)
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rx_rec_hdr = Record(_eb_rec_hdr)
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tx_rec_hdr = Record(_eb_rec_hdr)
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rx_eb_hdr = Record(_eb_hdr)
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tx_eb_hdr = Record(_eb_hdr)
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self.comb += [
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rx_eb_hdr.raw_bits().eq(self.rx.payload.data),
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tx_eb_hdr.magic.eq(rx_eb_hdr.magic),
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tx_eb_hdr.ver.eq(_eb_ver),
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tx_eb_hdr.no_response.eq(1),
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tx_eb_hdr.addr_size.eq(4),
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tx_eb_hdr.data_size.eq(4),
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tx_eb_hdr.probe_res.eq(rx_eb_hdr.probe),
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rx_rec_hdr.raw_bits().eq(self.rx.payload.data),
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tx_rec_hdr.wca_cfg.eq(rx_rec_hdr.bca_cfg),
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tx_rec_hdr.wr_fifo.eq(rx_rec_hdr.rd_fifo),
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tx_rec_hdr.wr_cnt.eq(rx_rec_hdr.rd_cnt),
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tx_rec_hdr.sel.eq(rx_rec_hdr.sel),
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tx_rec_hdr.drop_cyc.eq(rx_rec_hdr.drop_cyc),
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]
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do_rx = Signal()
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self.rx_cyc = Signal()
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self.comb += [
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wbm.bus.sel.eq(rx_rec_hdr.sel),
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do_rx.eq(tag.writable & # tag is always written/read
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self.rx_cyc & self.rx.stb & # have data
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(wbm.fifo.we | ~wbm.bus.stb) & # stb finished or idle
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(wbm.bus.cyc | ~wbm.busy)), # in-cycle or idle
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self.rx.ack.eq(do_rx),
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cfg.fifo.din.eq(wbm.bus.adr),
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# no eb-cfg write support yet
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#cfg.dat_w.eq(wbm.bus.dat_w),
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#cfg.we.eq(wbm.bus.we),
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cfg.errreg.eq(wbm.errreg),
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]
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cur_rx_rec_hdr = Record(_eb_rec_hdr)
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cur_tx_rec_hdr = Record(_eb_rec_hdr)
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do_rec = Signal()
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do_adr = Signal()
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do_write = Signal()
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do_read = Signal()
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wr_adr = Signal(flen(wbm.bus.adr))
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old_rx_cyc = Signal()
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self.sync += [
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wbm.bus.stb.eq(wbm.bus.stb & ~wbm.fifo.we),
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wbm.bus.cyc.eq(wbm.bus.cyc & (
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~cur_rx_rec_hdr.drop_cyc |
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(cur_rx_rec_hdr.wr_cnt > 0) |
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(cur_rx_rec_hdr.rd_cnt > 0))),
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If(do_rec,
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cur_rx_rec_hdr.eq(rx_rec_hdr),
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cur_tx_rec_hdr.eq(tx_rec_hdr),
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),
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If(do_adr,
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wr_adr.eq(self.rx.payload.data[2:]),
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),
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If(do_write,
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If(cur_rx_rec_hdr.wca_cfg,
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cfg.fifo.we.eq(1),
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).Else(
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wbm.bus.cyc.eq(1),
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wbm.bus.stb.eq(1),
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),
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wbm.bus.we.eq(1),
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wbm.bus.adr.eq(wr_adr),
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wbm.bus.dat_w.eq(self.rx.payload.data),
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If(~cur_rx_rec_hdr.wr_fifo,
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wr_adr.eq(wr_adr + 1),
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),
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cur_rx_rec_hdr.wr_cnt.eq(cur_rx_rec_hdr.wr_cnt - 1),
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),
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If(do_read,
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If(cur_rx_rec_hdr.rca_cfg,
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cfg.fifo.we.eq(1),
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).Else(
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wbm.bus.cyc.eq(1),
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wbm.bus.stb.eq(1),
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),
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wbm.bus.we.eq(0),
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wbm.bus.adr.eq(self.rx.payload.data[2:]),
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cur_rx_rec_hdr.rd_cnt.eq(cur_rx_rec_hdr.rd_cnt - 1),
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),
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If(~self.rx_cyc,
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wbm.bus.cyc.eq(0),
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),
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old_rx_cyc.eq(self.rx_cyc),
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]
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fsm = self.submodules.fsm = FSM()
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fsm.reset_state = "EB_HDR"
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fsm.act("EB_HDR",
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If(do_rx,
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tag.we.eq(1),
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If((rx_eb_hdr.magic != _eb_magic) |
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(rx_eb_hdr.ver !=_eb_ver),
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tag.din.eq(tags["SKIP_TX"]),
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NextState("DROP"),
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).Else(
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If(rx_eb_hdr.no_response,
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tag.din.eq(tags["SKIP_TX"]),
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).Else(
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tag.din.eq(tags["PASS_TX"]),
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pas.we.eq(1),
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pas.din.eq(tx_eb_hdr.raw_bits()),
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),
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If(rx_eb_hdr.probe,
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If(rx_eb_hdr.addr_size[2] &
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rx_eb_hdr.data_size[2],
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NextState("PROBE_ID"),
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).Else(
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NextState("PROBE_DROP"),
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),
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).Else(
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If((rx_eb_hdr.addr_size == 4) &
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(rx_eb_hdr.data_size == 4),
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NextState("CYC_HDR"),
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).Else(
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NextState("DROP"),
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),
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),
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),
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))
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fsm.act("PROBE_DROP",
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If(do_rx,
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tag.we.eq(1),
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tag.din.eq(tags["PASS_ON"]),
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pas.we.eq(1),
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pas.din.eq(self.rx.payload.data),
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NextState("DROP"),
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))
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fsm.act("PROBE_ID",
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If(do_rx,
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tag.we.eq(1),
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tag.din.eq(tags["PASS_ON"]),
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pas.we.eq(1),
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pas.din.eq(self.rx.payload.data),
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NextState("CYC_HDR"),
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))
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fsm.act("CYC_HDR",
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If(do_rx,
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do_rec.eq(1),
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tag.we.eq(1),
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tag.din.eq(tags["PASS_ON"]),
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pas.we.eq(1),
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If(rx_rec_hdr.wr_cnt != 0,
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NextState("WR_ADR"),
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).Else(
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pas.din.eq(tx_rec_hdr.raw_bits()),
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If(rx_rec_hdr.rd_cnt != 0,
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NextState("RD_ADR"),
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).Else(
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NextState("CYC_HDR"),
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),
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),
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))
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fsm.act("WR_ADR",
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If(do_rx,
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do_adr.eq(1),
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tag.we.eq(1),
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tag.din.eq(tags["PASS_ON"]),
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pas.we.eq(1),
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NextState("WRITE"),
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))
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fsm.act("WRITE",
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If(do_rx,
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do_write.eq(1),
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tag.we.eq(1),
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If(cur_rx_rec_hdr.wca_cfg,
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tag.din.eq(tags["CFG_IGN"]),
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).Else(
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wbm.active.eq(1),
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tag.din.eq(tags["WBM_IGN"]),
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),
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pas.we.eq(1),
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If(cur_rx_rec_hdr.wr_cnt == 1,
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pas.din.eq(cur_tx_rec_hdr.raw_bits()),
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If(cur_rx_rec_hdr.rd_cnt != 0,
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NextState("RD_ADR"),
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).Else(
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NextState("CYC_HDR"),
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),
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),
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))
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fsm.act("RD_ADR",
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If(do_rx,
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tag.we.eq(1),
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tag.din.eq(tags["PASS_ON"]),
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pas.we.eq(1),
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pas.din.eq(self.rx.payload.data),
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NextState("READ"),
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))
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fsm.act("READ",
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If(do_rx,
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do_read.eq(1),
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tag.we.eq(1),
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If(cur_rx_rec_hdr.rca_cfg,
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tag.din.eq(tags["CFG_REQ"]),
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).Else(
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wbm.active.eq(1),
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tag.din.eq(tags["WBM_REQ"]),
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),
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If(cur_rx_rec_hdr.rd_cnt == 1,
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NextState("CYC_HDR"),
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),
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))
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fsm.act("DROP",
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#If(do_rx,
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# tag.we.eq(1),
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# tag.din.eq(tags["PASS_ON"]),
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# pas.we.eq(1),
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#)
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)
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for state in fsm.actions:
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fsm.act(state, If(~self.rx_cyc, NextState("EB_HDR")))
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self.comb += [
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If(~self.rx_cyc,
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Cat(do_rec, do_adr, do_write, do_read).eq(0),
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Cat(wbm.active, pas.we).eq(0),
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If(old_rx_cyc,
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tag.we.eq(1),
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tag.din.eq(tags["DROP_TX"]),
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),
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)]
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class Slave(Module):
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def __init__(self, sdb_addr, timeout):
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tags = dict((k, i) for i, k in enumerate(
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"DROP_TX SKIP_TX PASS_TX PASS_ON CFG_REQ "
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"CFG_IGN WBM_REQ WBM_IGN".split()))
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tag_width = flen(Signal(max=len(tags)))
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self.submodules.pas = SyncFIFO(_eb_width, _eb_queue_len)
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self.submodules.cfg = Config(sdb_addr)
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self.submodules.wbm = WishboneMaster(timeout)
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self.submodules.tag = SyncFIFO(tag_width, _eb_queue_len)
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self.submodules.rxfsm = Receive(self.pas, self.cfg,
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self.wbm, self.tag, tags)
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self.rx = self.rxfsm.rx
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self.rx_cyc = self.rxfsm.rx_cyc
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self.submodules.txmux = Transmit(self.pas, self.cfg,
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self.wbm.fifo, self.tag, tags)
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self.tx = self.txmux.tx
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self.tx_skip = self.txmux.tx_skip
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self.tx_cyc = self.txmux.tx_cyc
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self.busy = self.wbm.busy
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class Converter(Module):
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def __init__(self, raw_width, graph, **slave_kwargs):
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raw_layout = [("data", raw_width)]
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pack_factor = _eb_width//raw_width
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self.rx = Sink(raw_layout)
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rx_pack = Pack(raw_layout, pack_factor)
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rx_cast = Cast(pack_layout(raw_layout, pack_factor), _eb_layout)
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self.submodules.slave = Slave(**slave_kwargs)
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tx_cast = Cast(_eb_layout, pack_layout(raw_layout, pack_factor))
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tx_unpack = Unpack(pack_factor, raw_layout)
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self.tx = Source(raw_layout)
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graph.add_connection(self.rx, rx_pack)
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graph.add_connection(rx_pack, rx_cast)
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graph.add_connection(rx_cast, self.slave.rx)
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graph.add_connection(self.slave.tx, tx_cast)
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graph.add_connection(tx_cast, tx_unpack)
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graph.add_connection(tx_unpack, self.tx)
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class SimTx(SimActor):
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def __init__(self, data):
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self.tx = Source(_eb_layout)
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SimActor.__init__(self, self.gen(data))
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def gen(self, data):
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for i in data:
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yield Token("tx", {"data": i})
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print("eb tx", hex(i))
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|
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class SimRx(SimActor):
|
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def __init__(self):
|
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self.rx = Sink(_eb_layout)
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self.recv = []
|
|
SimActor.__init__(self, self.gen())
|
|
|
|
def gen(self):
|
|
while True:
|
|
t = Token("rx")
|
|
yield t
|
|
print("eb rx", hex(t.value["data"]))
|
|
self.recv.append(t.value["data"])
|
|
|
|
class TB(Module):
|
|
def __init__(self, data):
|
|
ebm_tx = SimTx(data)
|
|
ebm_rx = SimRx()
|
|
self.slave = Slave(0x200, 10)
|
|
g = DataFlowGraph()
|
|
g.add_connection(ebm_tx, self.slave)
|
|
g.add_connection(self.slave, ebm_rx)
|
|
self.submodules.graph = CompositeActor(g)
|
|
self.submodules.cfg_master = wishbone.Initiator(self.gen_cfg_reads())
|
|
self.submodules.cfg_tap = wishbone.Tap(self.slave.cfg.bus,
|
|
lambda l: print("cfg", l))
|
|
self.submodules.wbm_tap = wishbone.Tap(self.slave.wbm.bus,
|
|
lambda l: print("wbm", l))
|
|
self.submodules.xbar = wishbone.Crossbar(
|
|
[self.cfg_master.bus, self.slave.wbm.bus],
|
|
[
|
|
(lambda a: a[6:] == 0x0, wishbone.Target(
|
|
wishbone.TargetModel()).bus),
|
|
(lambda a: a[6:] == 0x1, self.slave.cfg.bus),
|
|
])
|
|
|
|
def gen_cfg_reads(self):
|
|
for a in range(0x40, 0x40+4):
|
|
t = TRead(a)
|
|
yield t
|
|
|
|
def do_simulation(self, s):
|
|
#s.interrupt = self.cfg_master.done
|
|
s.wr(self.slave.rx_cyc, int(s.cycle_counter < 200))
|
|
|
|
class MyStruct(object):
|
|
_data = None
|
|
_fmt = "!"
|
|
|
|
def __init__(self, **kwargs):
|
|
self.data = self._data(**kwargs)
|
|
|
|
def __bytes__(self):
|
|
return struct.pack(self._fmt, *self.data)
|
|
|
|
class EbHeader(MyStruct):
|
|
_data = namedtuple("eb_hdr", "magic ver size")
|
|
_fmt = "!HBB"
|
|
|
|
def __init__(self, probe_id=None, addr_size=4, data_size=4, records=[]):
|
|
no_response = not any(r.read for r in records)
|
|
probe = probe_id is not None
|
|
probe_res = False
|
|
MyStruct.__init__(self, magic=_eb_magic, ver=(_eb_ver<<4) |
|
|
(no_response<<2) | (probe_res<<1) | (probe<<0),
|
|
size=(addr_size<<4) | (data_size<<0))
|
|
self.probe = struct.pack("!I", probe_id) if probe else b""
|
|
self.records = records
|
|
|
|
def __bytes__(self):
|
|
return (MyStruct.__bytes__(self) + self.probe +
|
|
b"".join(map(bytes, self.records)))
|
|
|
|
class EbRecord(MyStruct):
|
|
_data = namedtuple("eb_rec", "flags sel wr_cnt rd_cnt")
|
|
_fmt = "!BBBB"
|
|
|
|
def __init__(self, sel=0xf, wr_adr=0, rd_adr=0, write=[], read=[],
|
|
bca_cfg=False, rca_cfg=False, rd_fifo=False, drop_cyc=False,
|
|
wca_cfg=False, wr_fifo=False):
|
|
MyStruct.__init__(self, sel=sel, wr_cnt=len(write),
|
|
rd_cnt=len(read), flags=(bca_cfg<<7) | (rca_cfg<<6) |
|
|
(rd_fifo<<5) | (drop_cyc<<3) | (wca_cfg<<2) |
|
|
(wr_fifo>>1))
|
|
self.wr_adr = wr_adr
|
|
self.write = write
|
|
self.rd_adr = rd_adr
|
|
self.read = read
|
|
|
|
def __bytes__(self):
|
|
b = MyStruct.__bytes__(self)
|
|
if self.write:
|
|
b += struct.pack("!I" + "I"*len(self.write), self.wr_adr,
|
|
*self.write)
|
|
if self.read:
|
|
b += struct.pack("!I" + "I"*len(self.read), self.rd_adr,
|
|
*self.read)
|
|
return b
|
|
|
|
def main():
|
|
from migen.sim.generic import Simulator, TopLevel
|
|
|
|
#from migen.fhdl import verilog
|
|
#s = Slave(0, 10)
|
|
#print(verilog.convert(s, ios={s.rx.payload.data, s.tx.payload.data,
|
|
# s.rx.stb, s.rx.ack, s.tx.stb, s.tx.ack}))
|
|
|
|
eb_pkt = EbHeader(records=[
|
|
EbRecord(wr_adr=0x10, write=[0x20, 0x21],
|
|
rd_adr=0x30, read=range(0, 8, 4)),
|
|
EbRecord(rd_adr=0x40, read=range(0x100, 0x100+32, 4),
|
|
drop_cyc=True),
|
|
EbRecord(rca_cfg=True, bca_cfg=True, rd_adr=0x50,
|
|
read=range(0, 0+8, 4), drop_cyc=True),
|
|
])
|
|
eb_pkt = bytes(eb_pkt)
|
|
eb_pkt = struct.unpack("!" + "I"*(len(eb_pkt)//4), eb_pkt)
|
|
tb = TB(eb_pkt)
|
|
sim = Simulator(tb, TopLevel("etherbone.vcd"))
|
|
sim.run(500)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main() |