90 lines
1.9 KiB
Verilog
90 lines
1.9 KiB
Verilog
/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module master #(
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parameter id = 0,
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parameter nreads = 10,
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parameter nwrites = 10,
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parameter p = 4
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) (
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input sys_clk,
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input sys_rst,
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output reg [31:0] dat_w,
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input [31:0] dat_r,
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output reg [29:0] adr,
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output reg we,
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output reg [3:0] sel,
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output cyc,
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output stb,
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input ack,
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output reg tend
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);
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integer rcounter;
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integer wcounter;
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reg active;
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assign cyc = active;
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assign stb = active;
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always @(posedge sys_clk) begin
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if(sys_rst) begin
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dat_w <= 0;
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adr <= 0;
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we <= 0;
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sel <= 0;
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active <= 0;
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rcounter = 0;
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wcounter = 0;
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tend <= 0;
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end else begin
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if(ack) begin
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if(~active)
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$display("[M%d] Spurious ack", id);
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else begin
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if(we)
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$display("[M%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
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else
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$display("[M%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
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end
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active <= 1'b0;
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end else if(~active) begin
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if(($random % p) == 0) begin
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adr <= (($random % 5) << (30-2)) + id;
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sel <= sel + 1;
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active <= 1'b1;
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if(($random % 2) == 0) begin
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/* Read */
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we <= 1'b0;
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rcounter = rcounter + 1;
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end else begin
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/* Write */
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we <= 1'b1;
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dat_w <= ($random << 16) + id;
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wcounter = wcounter + 1;
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end
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end
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end
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tend <= (rcounter >= nreads) && (wcounter >= nwrites);
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end
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end
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endmodule
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