149 lines
5.0 KiB
Python
149 lines
5.0 KiB
Python
#!/usr/bin/env python3
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import sys
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import os
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import argparse
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import subprocess
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import struct
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import importlib
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from mibuild.tools import write_to_file
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from migen.util.misc import autotype
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from migen.fhdl import verilog, edif
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from migen.fhdl.structure import _Fragment
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from migen.bank.description import CSRStatus
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from mibuild import tools
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from mibuild.xilinx.common import *
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from misoclib.soc import cpuif
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from misoclib.com.litepcie.common import *
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def _import(default, name):
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return importlib.import_module(default + "." + name)
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def _get_args():
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parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
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description="""\
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LitePCIe - based on Migen.
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This program builds and/or loads LitePCIe components.
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One or several actions can be specified:
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clean delete previous build(s).
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build-rtl build verilog rtl.
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build-bitstream build-bitstream build FPGA bitstream.
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build-csr-csv save CSR map into CSV file.
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build-csr-header save CSR map into C header file.
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load-bitstream load bitstream into volatile storage.
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all clean, build-csr-csv, build-bitstream, load-bitstream.
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""")
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parser.add_argument("-t", "--target", default="dma", help="Core type to build")
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parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
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parser.add_argument("-p", "--platform", default=None, help="platform to build for")
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parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
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parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
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parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
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parser.add_argument("--csr_header", default="../software/linux/kernel/csr.h", help="C header file to save the CSR map into")
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parser.add_argument("action", nargs="+", help="specify an action")
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return parser.parse_args()
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# Note: misoclib need to be installed as a python library
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if __name__ == "__main__":
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args = _get_args()
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# create top-level Core object
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target_module = _import("targets", args.target)
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if args.sub_target:
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top_class = getattr(target_module, args.sub_target)
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else:
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top_class = target_module.default_subtarget
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if args.platform is None:
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platform_name = top_class.default_platform
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else:
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platform_name = args.platform
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platform_module = _import("mibuild.platforms", platform_name)
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platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
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platform = platform_module.Platform(**platform_kwargs)
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build_name = top_class.__name__.lower() + "-" + platform_name
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top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
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soc = top_class(platform, **top_kwargs)
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soc.finalize()
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memory_regions = soc.get_memory_regions()
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csr_regions = soc.get_csr_regions()
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# decode actions
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action_list = ["clean", "build-csr-csv", "build-csr-header", "build-bitstream", "load-bitstream", "all"]
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actions = {k: False for k in action_list}
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for action in args.action:
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if action in actions:
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actions[action] = True
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else:
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print("Unknown action: "+action+". Valid actions are:")
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for a in action_list:
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print(" "+a)
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sys.exit(1)
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print("""
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__ _ __ ______ __
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/ / (_) /____ / __/ /_/ /
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/ /__/ / __/ -_) _// __/ _ \\
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/____/_/\__/\__/___/\__/_//_/
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A small footprint and configurable PCIe
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core powered by Migen
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====== Building options: ======
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Platform: {}
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Target: {}
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Subtarget: {}
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System Clk: {} MHz
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===============================""".format(
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platform_name,
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args.target,
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top_class.__name__,
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soc.clk_freq/1000000
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)
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)
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# dependencies
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if actions["all"]:
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actions["build-csr-csv"] = True
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actions["build-csr-header"] = True
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actions["build-bitstream"] = True
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actions["load-bitstream"] = True
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if actions["build-bitstream"]:
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actions["build-csr-csv"] = True
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actions["build-csr-header"] = True
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actions["build-bitstream"] = True
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actions["load-bitstream"] = True
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if actions["clean"]:
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subprocess.call(["rm", "-rf", "build/*"])
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if actions["build-csr-csv"]:
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csr_csv = cpuif.get_csr_csv(csr_regions)
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write_to_file(args.csr_csv, csr_csv)
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if actions["build-csr-header"]:
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csr_header = cpuif.get_csr_header(csr_regions, soc.get_constants(), with_access_functions=False)
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write_to_file(args.csr_header, csr_header)
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if actions["build-bitstream"]:
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vns = platform.build(soc, build_name=build_name)
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if hasattr(soc, "do_exit") and vns is not None:
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if hasattr(soc.do_exit, '__call__'):
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soc.do_exit(vns)
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if actions["load-bitstream"]:
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prog = platform.create_programmer()
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prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
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