105 lines
3.4 KiB
Python
105 lines
3.4 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import CSRStatus
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def get_cpu_mak(cpu_type):
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if cpu_type == "lm32":
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cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled"
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elif cpu_type == "or1k":
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cpuflags = "-mhard-mul -mhard-div"
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else:
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raise ValueError("Unsupported CPU type: "+cpu_type)
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return "CPU={}\nCPUFLAGS={}\n".format(cpu_type, cpuflags)
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def get_linker_output_format(cpu_type):
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return "OUTPUT_FORMAT(\"elf32-{}\")\n".format(cpu_type)
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def get_linker_regions(regions):
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r = "MEMORY {\n"
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for name, origin, length in regions:
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r += "\t{} : ORIGIN = 0x{:08x}, LENGTH = 0x{:08x}\n".format(name, origin, length)
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r += "}\n"
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return r
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def get_mem_header(regions, flash_boot_address):
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r = "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n"
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for name, base, size in regions:
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r += "#define {name}_BASE 0x{base:08x}\n#define {name}_SIZE 0x{size:08x}\n\n".format(name=name.upper(), base=base, size=size)
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if flash_boot_address is not None:
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r += "#define FLASH_BOOT_ADDRESS 0x{:08x}\n\n".format(flash_boot_address)
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r += "#endif\n"
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return r
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def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
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r = ""
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r += "#define CSR_"+reg_name.upper()+"_ADDR "+hex(reg_base)+"\n"
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r += "#define CSR_"+reg_name.upper()+"_SIZE "+str(nwords)+"\n"
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size = nwords*busword
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if size > 64:
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return r
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elif size > 32:
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ctype = "unsigned long long int"
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elif size > 16:
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ctype = "unsigned int"
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elif size > 8:
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ctype = "unsigned short int"
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else:
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ctype = "unsigned char"
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r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
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if size > 1:
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r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
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for byte in range(1, nwords):
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r += "\tr <<= "+str(busword)+";\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
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r += "\treturn r;\n}\n"
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else:
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r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
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if not read_only:
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r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
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for word in range(nwords):
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shift = (nwords-word-1)*busword
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if shift:
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value_shifted = "value >> "+str(shift)
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else:
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value_shifted = "value"
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r += "\tMMPTR("+hex(reg_base+4*word)+") = "+value_shifted+";\n"
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r += "}\n"
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return r
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def get_csr_header(csr_base, bank_array, interrupt_map):
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r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
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for name, csrs, mapaddr, rmap in bank_array.banks:
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r += "\n/* "+name+" */\n"
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reg_base = csr_base + 0x800*mapaddr
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r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
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busword = flen(rmap.bus.dat_w)
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for csr in csrs:
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nr = (csr.size + busword - 1)//busword
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r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, busword, isinstance(csr, CSRStatus))
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reg_base += 4*nr
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try:
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interrupt_nr = interrupt_map[name]
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except KeyError:
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pass
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else:
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r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
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for name, memory, mapaddr, mmap in bank_array.srams:
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mem_base = csr_base + 0x800*mapaddr
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fullname = name + "_" + memory.name_override
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r += "#define "+fullname.upper()+"_BASE "+hex(mem_base)+"\n"
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r += "\n#endif\n"
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return r
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def get_csr_csv(csr_base, bank_array):
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r = ""
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for name, csrs, mapaddr, rmap in bank_array.banks:
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reg_base = csr_base + 0x800*mapaddr
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busword = flen(rmap.bus.dat_w)
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for csr in csrs:
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nr = (csr.size + busword - 1)//busword
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r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, reg_base, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
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reg_base += 4*nr
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return r
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