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8b41ab3a5f
litex
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misoclib
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soc
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Sebastien Bourdeauducq
176b9240a9
soc: use new ModuleTransformer API
2015-04-06 23:52:34 +08:00
..
__init__.py
soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
2015-04-03 12:45:32 +02:00
cpuif.py
soc/cpuif: fix CSR base generation for memories (name is already fullname)
2015-04-03 13:57:37 +02:00
sdram.py
soc: use new ModuleTransformer API
2015-04-06 23:52:34 +08:00