Florent Kermarrec 6216bd4e99 cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation.		2024-04-15 10:32:13 +02:00
..
__init__.py	…
test_avalon_mm.py	Merge branch 'master' into avalon-burst-test	2023-05-10 11:12:30 +02:00
test_axi.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_lite.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_stream.py	test: Add minimal test_axi_stream test (Just syntax check for now).	2022-09-08 11:53:05 +02:00
test_bitbang.py	…
test_clock.py	…
test_code_8b10b.py	…
test_cpu.py	test: Reinstate microwatt and neorv32	2023-02-27 17:46:41 +10:30
test_csr.py	test_csr: test cases for issue	2023-10-27 13:05:51 +11:00
test_ecc.py	…
test_emif.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_fifosyncmacro.py	…
test_gearbox.py	…
test_hyperbus.py	cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation.	2024-04-15 10:32:13 +02:00
test_i2s.py	…
test_icap.py	…
test_led.py	…
test_packet.py	…
test_prbs.py	…
test_reduce.py	gen/common/Reduce: Add ADD support.	2022-10-28 19:13:27 +02:00
test_spi.py	…
test_spi_mmap.py	test: Add minimal test_spi_mmap with simulation of SPIMaster.	2023-08-04 17:51:22 +02:00
test_spi_opi.py	…
test_stream.py	stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.	2022-09-07 08:59:37 +02:00
test_timer.py	…
test_wishbone.py	test/test_wishbone: Improve origin_region_remap_test to test more complex remapping.	2024-02-28 19:11:55 +01:00