224 lines
7.1 KiB
Python
224 lines
7.1 KiB
Python
import os, atexit
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from litesata.common import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib import identifier
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from litescope.common import *
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from litescope.bridge.uart2wb import LiteScopeUART2WB
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from litescope.frontend.la import LiteScopeLA
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from litescope.core.port import LiteScopeTerm
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from litesata.common import *
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from litesata.phy import LiteSATAPHY
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from litesata import LiteSATA
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.reset = Signal()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 166MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
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]
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class GenSoC(Module):
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csr_base = 0x00000000
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csr_data_width = 32
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csr_map = {
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"bridge": 0,
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"identifier": 1,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.clk_freq = clk_freq
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# UART <--> Wishbone bridge
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self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.bridge.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class BISTLeds(Module):
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def __init__(self, platform, sata_phy):
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# 1Hz blinking leds (sata_rx and sata_tx clocks)
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sata_rx_led = platform.request("user_led", 0)
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sata_tx_led = platform.request("user_led", 1)
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sata_rx_cnt = Signal(32)
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sata_tx_cnt = Signal(32)
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sata_freq = int(frequencies[sata_phy.revision]*1000*1000)
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self.sync.sata_rx += \
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If(sata_rx_cnt == 0,
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sata_rx_led.eq(~sata_rx_led),
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sata_rx_cnt.eq(sata_freq//2)
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).Else(
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sata_rx_cnt.eq(sata_rx_cnt-1)
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)
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self.sync.sata_tx += \
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If(sata_tx_cnt == 0,
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sata_tx_led.eq(~sata_tx_led),
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sata_tx_cnt.eq(sata_freq//2)
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).Else(
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sata_tx_cnt.eq(sata_tx_cnt-1)
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)
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# ready leds (crg and ctrl)
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self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
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self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
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class BISTSoC(GenSoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"sata": 10,
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}
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csr_map.update(GenSoC.csr_map)
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def __init__(self, platform):
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clk_freq = 166*1000000
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GenSoC.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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# SATA PHY/Core/Frontend
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self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
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self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
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self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
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# Status Leds
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self.submodules.leds = BISTLeds(platform, self.sata_phy)
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class BISTSoCDevel(BISTSoC, AutoCSR):
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csr_map = {
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"la": 20
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}
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csr_map.update(BISTSoC.csr_map)
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def __init__(self, platform):
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BISTSoC.__init__(self, platform)
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self.sata_core_link_rx_fsm_state = Signal(4)
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self.sata_core_link_tx_fsm_state = Signal(4)
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self.sata_core_transport_rx_fsm_state = Signal(4)
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self.sata_core_transport_tx_fsm_state = Signal(4)
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self.sata_core_command_rx_fsm_state = Signal(4)
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self.sata_core_command_tx_fsm_state = Signal(4)
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debug = (
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self.sata_phy.ctrl.ready,
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self.sata_phy.source.stb,
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self.sata_phy.source.data,
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self.sata_phy.source.charisk,
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self.sata_phy.sink.stb,
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self.sata_phy.sink.data,
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self.sata_phy.sink.charisk,
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self.sata.core.command.sink.stb,
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self.sata.core.command.sink.sop,
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self.sata.core.command.sink.eop,
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self.sata.core.command.sink.ack,
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self.sata.core.command.sink.write,
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self.sata.core.command.sink.read,
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self.sata.core.command.sink.identify,
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self.sata.core.command.source.stb,
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self.sata.core.command.source.sop,
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self.sata.core.command.source.eop,
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self.sata.core.command.source.ack,
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self.sata.core.command.source.write,
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self.sata.core.command.source.read,
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self.sata.core.command.source.identify,
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self.sata.core.command.source.failed,
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self.sata.core.command.source.data,
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self.sata_core_link_rx_fsm_state,
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self.sata_core_link_tx_fsm_state,
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self.sata_core_transport_rx_fsm_state,
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self.sata_core_transport_tx_fsm_state,
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self.sata_core_command_rx_fsm_state,
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self.sata_core_command_tx_fsm_state,
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)
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self.submodules.la = LiteScopeLA(debug, 2048)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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atexit.register(self.exit, platform)
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def do_finalize(self):
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BISTSoC.do_finalize(self)
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self.comb += [
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self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state),
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self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state),
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self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state),
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self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state),
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self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state),
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self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
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]
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def exit(self, platform):
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if platform.vns is not None:
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self.la.export(platform.vns, "../test/la.csv")
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default_subtarget = BISTSoC
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