152 lines
4.7 KiB
Python
152 lines
4.7 KiB
Python
from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE
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# Bank 34 and 35 voltage depend on J18 jumper setting
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_io = [
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("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("P16"), IOStandard("LVCMOS18")), # center
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("user_btn", 1, Pins("R16"), IOStandard("LVCMOS18")), # down
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("user_btn", 2, Pins("N15"), IOStandard("LVCMOS18")), # left
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("user_btn", 3, Pins("R18"), IOStandard("LVCMOS18")), # right
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("user_btn", 4, Pins("T18"), IOStandard("LVCMOS18")), # up
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("user_sw", 0, Pins("F22"), IOStandard("LVCMOS18")),
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("user_sw", 1, Pins("G22"), IOStandard("LVCMOS18")),
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("user_sw", 2, Pins("H22"), IOStandard("LVCMOS18")),
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("user_sw", 3, Pins("F21"), IOStandard("LVCMOS18")),
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("user_sw", 4, Pins("H19"), IOStandard("LVCMOS18")),
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("user_sw", 5, Pins("H18"), IOStandard("LVCMOS18")),
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("user_sw", 6, Pins("H17"), IOStandard("LVCMOS18")),
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("user_sw", 7, Pins("M15"), IOStandard("LVCMOS18")),
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("user_led", 0, Pins("T22"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("T21"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("U22"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("U21"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("V22"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("W22"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("U19"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("U14"), IOStandard("LVCMOS33")),
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# A
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("pmod", 0, Pins("Y11 AA11 Y10 AA9 AB11 AB10 AB9 AA8"),
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IOStandard("LVCMOS33")),
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# B
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("pmod", 1, Pins("W12 W11 V10 W8 V12 W10 V9 V8"),
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IOStandard("LVCMOS33")),
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# C
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("pmod", 2,
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Subsignal("n", Pins("AB6 AA4 T6 U4")),
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Subsignal("p", Pins("AB7 Y4 R6 T4")),
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IOStandard("LVCMOS33")),
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# D
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("pmod", 3,
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Subsignal("n", Pins("W7 V4 W5 U5")),
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Subsignal("p", Pins("V7 V5 W6 U6")),
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IOStandard("LVCMOS33")),
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("audio", 0,
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Subsignal("adr", Pins("AB1 Y5")),
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Subsignal("gpio", Pins("Y8 AA7 AA6 Y6")),
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Subsignal("mclk", Pins("AB2")),
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Subsignal("sck", Pins("AB4")),
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Subsignal("sda", Pins("AB5")),
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IOStandard("LVCMOS33")),
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("oled", 0,
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Subsignal("dc", Pins("U10")),
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Subsignal("res", Pins("U9")),
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Subsignal("sclk", Pins("AB12")),
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Subsignal("sdin", Pins("AA12")),
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Subsignal("vbat", Pins("U11")),
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Subsignal("vdd", Pins("U12")),
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IOStandard("LVCMOS33")),
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("hdmi", 0,
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Subsignal("clk", Pins("W18")),
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Subsignal("d", Pins(
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"Y13 AA13 AA14 Y14 AB15 AB16 AA16 AB17 "
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"AA17 Y15 W13 W15 V15 U17 V14 V13")),
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Subsignal("de", Pins("U16")),
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Subsignal("hsync", Pins("V17")),
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Subsignal("vsync", Pins("W17")),
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Subsignal("int", Pins("W16")),
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Subsignal("scl", Pins("AA18")),
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Subsignal("sda", Pins("Y16")),
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Subsignal("spdif", Pins("U15")),
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Subsignal("spdifo", Pins("Y18")),
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IOStandard("LVCMOS33")),
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("netic16", 0,
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Subsignal("w20", Pins("W20")),
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Subsignal("w21", Pins("W21")),
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IOStandard("LVCMOS33")),
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("vga", 0,
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Subsignal("r", Pins("V20 U20 V19 V18")),
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Subsignal("g", Pins("AB22 AA22 AB21 AA21")),
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Subsignal("b", Pins("Y21 Y20 AB20 AB19")),
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Subsignal("hsync_n", Pins("AA19")),
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Subsignal("vsync_n", Pins("Y19")),
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IOStandard("LVCMOS33")),
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("usb_otg", 0,
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Subsignal("vbusoc", Pins("L16")),
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Subsignal("reset_n", Pins("G17")),
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IOStandard("LVCMOS18")),
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("pudc_b", 0, Pins("K16"), IOStandard("LVCMOS18")),
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("xadc", 0,
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Subsignal("gio", Pins("H15 R15 K15 J15")),
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Subsignal("ad0_n", Pins("E16")),
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Subsignal("ad0_p", Pins("F16")),
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Subsignal("ad8_n", Pins("D17")),
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Subsignal("ad8_p", Pins("D16")),
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IOStandard("LVCMOS18")),
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("fmc_clocks", 0,
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Subsignal("clk0_n", Pins("L19")),
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Subsignal("clk0_p", Pins("L18")),
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Subsignal("clk1_n", Pins("C19")),
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Subsignal("clk1_p", Pins("D18")),
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IOStandard("LVCMOS18")),
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("fmc", 0,
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Subsignal("scl", Pins("R7")),
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Subsignal("sda", Pins("U7")),
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Subsignal("prsnt", Pins("AB14")),
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# 0, 1, 17, 18 can be clock signals
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Subsignal("la_n", Pins(
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"M20 N20 P18 P22 M22 K18 L22 T17 "
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"J22 R21 T19 N18 P21 M17 K20 J17 "
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"K21 B20 C20 G16 G21 E20 F19 D15 "
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"A19 C22 E18 D21 A17 C18 B15 B17 "
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"A22 B22")),
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Subsignal("la_p", Pins(
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"M19 N19 P17 N22 M21 J18 L21 T16 "
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"J21 R20 R19 N17 P20 L17 K19 J16 "
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"J20 B19 D20 G15 G20 E19 G19 E15 "
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"A18 D22 F18 E21 A16 C17 C15 B16 "
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"A21 B21")),
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IOStandard("LVCMOS18")),
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
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lambda p: CRG_SE(p, "clk100", None))
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def do_finalize(self, fragment):
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try:
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self.add_platform_command("""
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NET "{clk100}" TNM_NET = "GRPclk100";
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TIMESPEC "TSclk100" = PERIOD "GRPclk100" 10 ns HIGH 50%;
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""", clk100=self.lookup_request("clk100"))
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except ConstraintError:
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pass
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