Jędrzej Boczar 8fd3e74ec9 bios/sdram: add firmware for reading SPD EEPROM		2020-05-21 14:07:42 +02:00
..
cores	cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.	2020-05-18 17:30:42 +02:00
doc	soc/doc/csr: allow CSRField.reset to be a Migen Constant.	2020-03-23 18:47:41 +01:00
integration	software: create liblitescard and move sdcard init/test code to it.	2020-05-18 22:49:12 +02:00
interconnect	integration/soc: review/simplify changes for standalone cores.	2020-05-12 16:18:26 +02:00
software	bios/sdram: add firmware for reading SPD EEPROM	2020-05-21 14:07:42 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00