litex/misoclib/soc
2015-03-03 09:55:25 +01:00
..
__init__.py soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :) 2015-03-01 18:25:47 +01:00
cpuif.py cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
sdram.py sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy 2015-03-03 09:55:25 +01:00