17 lines
414 B
Python
17 lines
414 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Tristate
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from migen.fhdl.module import Module
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self, n=6):
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self.pad = Signal(n)
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self.o = Signal(n)
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self.oe = Signal()
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self.i = Signal(n)
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self.specials += Tristate(self.pad, self.o, self.oe, self.i)
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e = Example()
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print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
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