Yves Delley 1dcd2ac1c0 fixed bug in value_bits_sign of mul operatiors		2015-09-10 10:53:26 -07:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
bitcontainer.py	fixed bug in value_bits_sign of mul operatiors	2015-09-10 10:53:26 -07:00
conv_output.py	introduce conversion output object (prevents file IO in FHDL backends)	2015-04-08 20:28:23 +08:00
decorators.py	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
edif.py	global: pep8 (E231)	2015-04-13 20:50:03 +02:00
module.py	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
namer.py	fhdl/verilog: add reserved keywords	2015-05-23 14:01:08 +02:00
simplify.py	global: pep8 (E261, E271)	2015-04-13 21:21:30 +02:00
specials.py	fhdl/specials: add Keep SynthesisDirective	2015-06-23 16:14:42 +02:00
std.py	global: pep8 (replace tabs with spaces)	2015-04-13 20:07:07 +02:00
structure.py	resetless -> reset_less	2015-07-27 11:46:11 +08:00
tools.py	resetless -> reset_less	2015-07-27 11:46:11 +08:00
tracer.py	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
verilog.py	fhdl/verilog: add reserved keywords	2015-05-23 14:01:08 +02:00
visit.py	global: pep8 (E302)	2015-04-13 20:45:35 +02:00