Florent Kermarrec f03d862c06 targets: switch to add_ethernet method instead of EthernetSoC.		2020-03-20 23:46:15 +01:00
..
__init__.py
test_axi.py	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
test_bitbang.py
test_clock.py	test: add initial (minimal) test for clock abstraction modules.	2020-03-13 12:38:23 +01:00
test_code_8b10b.py
test_csr.py
test_ecc.py
test_gearbox.py
test_hyperbus.py
test_i2s.py	soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.	2020-02-06 17:00:04 +01:00
test_icap.py
test_packet.py	test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer	2019-11-16 14:39:18 +01:00
test_prbs.py
test_spi.py
test_spi_opi.py	soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)	2020-02-06 17:58:01 +01:00
test_stream.py	interconnect/stream: add PipeValid and PipeWait to cut timing paths.	2020-01-29 18:27:29 +01:00
test_targets.py	targets: switch to add_ethernet method instead of EthernetSoC.	2020-03-20 23:46:15 +01:00