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93de581931
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
48 lines
1.5 KiB
Python
48 lines
1.5 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.io import CRG
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from misoclib.soc import SoC, mem_decoder
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from misoclib.com.liteeth.phy import LiteEthPHY
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from misoclib.com.liteeth.mac import LiteEthMAC
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class BaseSoC(SoC):
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def __init__(self, platform, **kwargs):
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SoC.__init__(self, platform,
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clk_freq=int((1/(platform.default_clk_period))*1000000000),
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integrated_rom_size=0x8000,
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integrated_main_ram_size=16*1024,
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**kwargs)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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class MiniSoC(BaseSoC):
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csr_map = {
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"ethphy": 20,
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"ethmac": 21
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
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platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone",
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with_hw_preamble_crc=False)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
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default_subtarget = BaseSoC
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