111 lines
2.1 KiB
Python
111 lines
2.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.bus import csr
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from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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from miscope.recorder import *
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arm_done = False
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dat = 0
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rec_done = False
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dat_rdy = False
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rec_size = 128
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def csr_transactions():
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# Reset
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yield TWrite(REC_RST_BASE, 1)
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yield TWrite(REC_RST_BASE, 0)
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# RLE
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yield TWrite(REC_RLE_BASE, 1)
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# Size
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yield TWrite(REC_SIZE_BASE + 0, 0)
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yield TWrite(REC_SIZE_BASE + 1, rec_size)
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# Offset
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yield TWrite(REC_OFFSET_BASE + 0, 0)
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yield TWrite(REC_OFFSET_BASE + 1, 0)
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# Arm
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yield TWrite(REC_ARM_BASE, 1)
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yield TWrite(REC_ARM_BASE, 0)
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for t in range(10):
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yield None
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global arm_done
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arm_done = True
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global rec_done
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while not rec_done:
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yield None
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global dat_rdy
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for t in range(rec_size):
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yield TWrite(REC_READ_BASE, 1)
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dat_rdy = False
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yield TWrite(REC_READ_BASE, 0)
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yield TRead(REC_READ_DATA_BASE + 0)
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yield TRead(REC_READ_DATA_BASE + 1)
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yield TRead(REC_READ_DATA_BASE + 2)
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yield TRead(REC_READ_DATA_BASE + 3)
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dat_rdy = True
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dat_rdy = False
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for t in range(100):
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yield None
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def main():
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# Csr Master
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csr_master0 = csr.Initiator(csr_transactions())
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# Recorder
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recorder0 = Recorder(32, 1024)
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# Csr Interconnect
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csrcon0 = csr.Interconnect(csr_master0.bus,
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[
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recorder0.bank.bus
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])
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# Recorder Data
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def recorder_data(s):
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global arm_done
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if arm_done:
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s.wr(recorder0.hit, 1)
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arm_done = False
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global dat
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s.wr(recorder0.dat, dat//5)
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dat += 1
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global rec_done
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if s.rd(recorder0.sequencer.enable) == 0:
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rec_done = True
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if dat_rdy:
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print("%08X" %s.rd(recorder0._pull_dat.field.w))
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# Simulation
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def end_simulation(s):
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s.interrupt = csr_master0.done
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fragment = csr_master0.get_fragment()
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fragment += recorder0.get_fragment()
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fragment += csrcon0.get_fragment()
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fragment += Fragment(sim=[end_simulation])
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fragment += Fragment(sim=[recorder_data])
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sim = Simulator(fragment, TopLevel("tb_RecorderCsr.vcd"))
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sim.run(10000)
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main()
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print("Sim Done")
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input() |