44 lines
1.2 KiB
Python
44 lines
1.2 KiB
Python
import os
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import top
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# list Verilog sources before changing directory
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verilog_sources = []
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def add_core_dir(d):
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root = os.path.join("verilog", d)
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files = os.listdir(root)
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for f in files:
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if f[-2:] == ".v":
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verilog_sources.append(os.path.join(root, f))
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def add_core_files(d, files):
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for f in files:
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verilog_sources.append(os.path.join("verilog", d, f))
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add_core_dir("generic")
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add_core_dir("m1crg")
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add_core_dir("s6ddrphy")
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add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
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"jtag_tap_spartan6.v"])
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add_core_dir("minimac3")
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os.chdir("build")
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def str2file(filename, contents):
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f = open(filename, "w")
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f.write(contents)
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f.close()
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# generate source
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(src_verilog, src_ucf) = top.get()
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str2file("soc.v", src_verilog)
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str2file("soc.ucf", src_ucf)
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verilog_sources.append("build/soc.v")
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# generate XST project file
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xst_prj = ""
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for s in verilog_sources:
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xst_prj += "verilog work ../" + s + "\n"
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str2file("soc.prj", xst_prj)
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