93 lines
1.9 KiB
C
93 lines
1.9 KiB
C
#include <irq.h>
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#include <uart.h>
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#ifdef __or1k__
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#include <spr-defs.h>
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#endif
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#include <system.h>
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#include <generated/mem.h>
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#include <generated/csr.h>
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void flush_cpu_icache(void)
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{
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#if defined (__lm32__)
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asm volatile(
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"wcsr ICC, r0\n"
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"nop\n"
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"nop\n"
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"nop\n"
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"nop\n"
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);
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#elif defined (__or1k__)
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unsigned long iccfgr;
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unsigned long cache_set_size;
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unsigned long cache_ways;
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unsigned long cache_block_size;
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unsigned long cache_size;
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int i;
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iccfgr = mfspr(SPR_ICCFGR);
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cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
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cache_size = cache_set_size * cache_ways * cache_block_size;
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for (i = 0; i < cache_size; i += cache_block_size)
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mtspr(SPR_ICBIR, i);
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#else
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#error Unsupported architecture
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#endif
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}
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void flush_cpu_dcache(void)
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{
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#if defined (__lm32__)
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asm volatile(
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"wcsr DCC, r0\n"
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"nop\n"
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);
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#elif defined (__or1k__)
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unsigned long dccfgr;
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unsigned long cache_set_size;
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unsigned long cache_ways;
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unsigned long cache_block_size;
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unsigned long cache_size;
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int i;
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dccfgr = mfspr(SPR_DCCFGR);
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cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW);
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cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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cache_size = cache_set_size * cache_ways * cache_block_size;
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for (i = 0; i < cache_size; i += cache_block_size)
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mtspr(SPR_DCBIR, i);
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#else
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#error Unsupported architecture
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#endif
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}
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#ifdef CSR_WISHBONE2LASMI_BASE
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void flush_l2_cache(void)
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{
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unsigned int l2_nwords;
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unsigned int i;
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register unsigned int addr;
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register unsigned int dummy;
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l2_nwords = 1 << wishbone2lasmi_cachesize_read();
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for(i=0;i<2*l2_nwords;i++) {
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addr = MAIN_RAM_BASE + i*4;
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#ifdef __lm32__
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__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
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#else
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#warning TODO
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#endif
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}
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}
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#else
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void flush_l2_cache(void)
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{
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}
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#endif
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